ddr_T_main_Scheduler_DdrConf
DDR configuration definition.
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler | 0xF8000400 | 0xF8000408 |
Size: 32
Offset: 0x8
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
DDRCONF RW 0x0 |
||||||||||||||
ddr_T_main_Scheduler_DdrConf Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 4:0 | DDRCONF |
Selection of a configuration of mappings of address bits to memory device, bank, row, and column. <See SoC-specific DDR Conf documentation>
|
RW | 0x0 |