ddr_T_main_Scheduler_ReadLatency

         DDR Main Scheduler Read Latency Register

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler`	`0xF8000400`	`0xF8000414`

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`READLATENCY` `RW 0x3D`

ddr_T_main_Scheduler_ReadLatency Fields

Bit	Name	Description	Access	Reset
7:0	`READLATENCY`	The DRAM type-specific number of cycles from a scheduler request to a protocol controller response. This is a fixed value depending on the type of DRAM memory. <See SoC-specific memory controller documentation>.	`RW`	`0x3D`

Bit

Name

Description

Access

Reset

7:0

READLATENCY

The DRAM type-specific number of cycles from a scheduler request to a protocol controller response. This is a fixed value depending on the type of DRAM memory. <See SoC-specific memory controller documentation>.

RW

0x3D