ddr_T_main_Scheduler_DdrTiming 

         DDR timing definition.
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler 0xF8000400 0xF800040C

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BWRATIO

RW 0x1

WRTORD

RW 0xC

RDTOWR

RW 0x2

BURSTLEN

RW 0x3

WRTOMISS

RW 0x25

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WRTOMISS

RW 0x25

RDTOMISS

RW 0x15

ACTTOACT

RW 0x1F

ddr_T_main_Scheduler_DdrTiming Fields

Bit Name Description Access Reset
31 BWRATIO 
When set to zero, one DRAM clock cycle (two DDR transfers) is used to transfer each word of data. When set to one, two DRAM clock cycles (four DDR transfers) are used to transfer each word of data. This is applicable when half of a DRAM data bus width is used.
 RW 0x1
30:26 WRTORD 
The minimum number of scheduler clock cycles between the last DRAM Write command and a Read command (WL x tCkD + tWTR). tCkD is the DRAM clock period.
 RW 0xC
25:21 RDTOWR 
The minimum number of scheduler clock cycles between the last DRAM Read command and a Write command (DDR2: 2 x tCkD, DDR3: (RL - WL + 2) x tCkD). tCkD is the DRAM clock period.
 RW 0x2
20:18 BURSTLEN 
The DRAM burst duration on the DRAM data bus in scheduler clock cycles. Also equal to scheduler clock cycles between two DRAM commands (BL / 2 x tCkD). tCkD is the DRAM clock period.
 RW 0x3
17:12 WRTOMISS 
The minimum number of scheduler clock cycles between the last DRAM Write command and a new Read or Write command in another page of the same bank (WL x tCkD + tWR + tRP + tRCD). tCkD is the DRAM clock period.
 RW 0x25
11:6 RDTOMISS 
The minimum number of scheduler clock cycles between the last DRAM Read command and a new Read or Write command in another page of the same bank (tRTP + tRP + tRCD - BL x tCkD / 2). tCkD is the DRAM clock period.
 RW 0x15
5:0 ACTTOACT 
The minimum number of scheduler clock cycles between two consecutive DRAM Activate commands on the same bank (tRC/ tCkG). tCkG is the clock period of the SoC DRAM scheduler.
 RW 0x1F