ddr_T_main_Scheduler_DevToDev

         Timing values concerning device to device data bus ownership change, in Generic clock unit.

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler`	`0xF8000400`	`0xF800043C`

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`BUSWRTORD` `RW 0x2`		`BUSRDTOWR` `RW 0x2`		`BUSRDTORD` `RW 0x1`

ddr_T_main_Scheduler_DevToDev Fields

Bit	Name	Description	Access	Reset
5:4	`BUSWRTORD`	The number of cycles between the last write data to a device and the first read data of another device of a memory array with multiple ranks (2 x tCkD). tCkD is the DRAM clock period.	`RW`	`0x2`
3:2	`BUSRDTOWR`	The number of cycles between the last read data of a device and the first write data to another device of a memory array with multiple ranks (2 x tCkD). tCkD is the DRAM clock period.	`RW`	`0x2`
1:0	`BUSRDTORD`	The number of cycles between the last read data of a device and the first read data of another device of a memory array with multiple ranks (tCkD). tCkD is the DRAM clock period.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

5:4

BUSWRTORD

The number of cycles between the last write data to a device and the first read data of another device of a memory array with multiple ranks (2 x tCkD). tCkD is the DRAM clock period.

RW

0x2

3:2

BUSRDTOWR

The number of cycles between the last read data of a device and the first write data to another device of a memory array with multiple ranks (2 x tCkD). tCkD is the DRAM clock period.

RW

0x2

1:0

BUSRDTORD

The number of cycles between the last read data of a device and the first read data of another device of a memory array with multiple ranks (tCkD). tCkD is the DRAM clock period.

RW

0x1