ddr_T_main_Scheduler_Activate 

         Timing values concerning Activate commands, in Generic clock unit.
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler 0xF8000400 0xF8000438

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FAWBANK

RW 0x1

FAW

RW 0xF

RRD

RW 0x3

ddr_T_main_Scheduler_Activate Fields

Bit Name Description Access Reset
10 FAWBANK 
The number of Banks of a given device involved in the FAW period. Set to zero for 2-bank memories (WideIO). Set to one for memories with 4 banks or more (DDR).
 RW 0x1
9:4 FAW 
The number of cycles for the four bank activate (FAW) period (tFAW).
 RW 0xF
3:0 RRD 
'The number of cycles between two consecutive Activate commands on different Banks of the same device (tRRD).
 RW 0x3