ddr_scheduler_ddr_T_main_Scheduler Address Map

Module Instance	Base Address	End Address
`soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler`	`0xF8000400`	`0xF800047F`

Register	Offset	Width	Access	Reset Value	Description
`ddr_T_main_Scheduler_Id_CoreId`	`0x0`	`32`	`RO`	`0x6471BE02`	DDR Main Scheduler Core ID Register
`ddr_T_main_Scheduler_Id_RevisionId`	`0x4`	`32`	`RO`	`0x00014800`	DDR Main Scheduler Revision ID Register
`ddr_T_main_Scheduler_DdrConf`	`0x8`	`32`	`RW`	`0x00000000`	DDR configuration definition.
`ddr_T_main_Scheduler_DdrTiming`	`0xC`	`32`	`RW`	`0xB04E555F`	DDR timing definition.
`ddr_T_main_Scheduler_DdrMode`	`0x10`	`32`	`RW`	`0x00000000`	DDR mode definition.
`ddr_T_main_Scheduler_ReadLatency`	`0x14`	`32`	`RW`	`0x0000003D`	DDR Main Scheduler Read Latency Register
`ddr_T_main_Scheduler_Activate`	`0x38`	`32`	`RW`	`0x000004F3`	Timing values concerning Activate commands, in Generic clock unit.
`ddr_T_main_Scheduler_DevToDev`	`0x3C`	`32`	`RW`	`0x00000029`	Timing values concerning device to device data bus ownership change, in Generic clock unit.
`ddr_T_main_Scheduler_Ddr4Timing`	`0x40`	`32`	`RW`	`0x00000367`	Long timing for DDR4 Bank Group support.