spim Address Map

Module Instance Base Address End Address
i_spim_0_spim 0xFFDA4000 0xFFDA4FFF
i_spim_1_spim 0xFFDA5000 0xFFDFFFFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
ctrlr0 0x0 32 RW 0x7 
Control Register 0:
This register controls the serial data transfer. It is impossible to
write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
is enabled and disabled by writing to the SSIENR register.
ctrlr1 0x4 32 RW 0x0 
Control Register 1
This register exists only when the DW_apb_ssi is configured as a
master device. When the DW_apb_ssi is configured as a serial slave,
writing to this location has no effect; reading from this location
returns 0. Control register 1 controls the end of serial transfers
when in receive-only mode. It is impossible to write to this
register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled
and disabled by writing to the SSIENR register.
spienr 0x8 32 RW 0x0 
SSI Enable Register
mwcr 0xC 32 RW 0x0 
Microwire Control Register.
This register controls the direction of the data word for the half-duplex
Microwire serial protocol. It is impossible to write to this register
when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
writing to the SSIENR register.
ser 0x10 32 RW 0x0 
Slave Enable Register.
This register is valid only when the DW_apb_ssi is configured as a master
device. When the DW_apb_ssi is configured as a serial slave, writing to
this location has no effect; reading from this location returns 0. The
register enables the individual slave select output lines from the
DW_apb_ssi master. Up to 16 slave-select output pins are available on the
DW_apb_ssi master. You cannot write to this register when DW_apb_ssi is
busy and when SSI_EN = 1.
baudr 0x14 32 RW 0x0 
Baud Rate Select.
This register is valid only when the DW_apb_ssi is configured as a master
device. When the DW_apb_ssi is configured as a serial slave, writing to
this location has no effect; reading from this location returns 0. The
register derives the frequency of the serial clock that regulates the data
transfer. The 16-bit field in this register defines the ssi_clk divider
value. It is impossible to write to this register when the DW_apb_ssi is
enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR
register.
txftlr 0x18 32 RW 0x0 
Transmit FIFO Threshold Level.
This register controls the threshold value for the transmit FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
rxftlr 0x1C 32 RW 0x0 
Receive FIFO Threshold level.
This register controls the threshold value for the receive FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
txflr 0x20 32 RO 0x0 
Transmit FIFO Level Register
rxflr 0x24 32 RO 0x0 
Receive FIFO Level Register
sr 0x28 32 RO 0x6 
Status Register
imr 0x2C 32 RW 0x3F 
Interrupt Mask Register
isr 0x30 32 RO 0x0 
Interrupt Status Register
risr 0x34 32 RO 0x0 
Raw Interrupt StatusRegister
txoicr 0x38 32 RO 0x0 
Transmit FIFO Overflow Interrupt Clear Register
rxoicr 0x3C 32 RO 0x0 
Receive FIFO Overflow Interrupt Clear Register
rxuicr 0x40 32 RO 0x0 
Receive FIFO Underflow Interrupt Clear Register
icr 0x48 32 RO 0x0 
Interrupt Clear Register
dmacr 0x4C 32 RW 0x0 
DMA Control Register.
This register is only valid when DW_apb_ssi is configured with a set of
DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
not configured for DMA operation, this register will not exist and writing
to the register's address will have no effect; reading from this register
address will return zero. The register is used to enable the DMA
Controller interface operation.
dmatdlr 0x50 32 RW 0x0 
DMA Transmit Data Level.
This register is only valid when the DW_apb_ssi is configured with a set
of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
configured for DMA operation, this register will not exist and writing
to its address will have no effect; reading from its address will
return zero.
dmardlr 0x54 32 RW 0x0 
DMA Receive Data Level.
This register is only valid when DW_apb_ssi is configured with a set of
DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
for DMA operation, this register will not exist and writing to its address
will have no effect; reading from its address will return zero.
idr 0x58 32 RO 0x5510000 
Identification Register.
This register contains the peripherals identification code, which is
written into the register at configuration time using coreConsultant.
spi_version_id 0x5C 32 RW 0x3332322A 
coreKit Version ID Register
dr 0x60 32 RW 0x0 
The DW_apb_ssi data register is a 16-bit read/write buffer for the
transmit/receive FIFOs. When the register is read, data in the receive
FIFO buffer is accessed. When it is written to, data are moved into the
transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are
reset when SSI_EN = 0.
rx_sample_dly 0xF0 32 RW 0x0 
RX Sample Delay.
This register is only valid when the DW_apb_ssi is configured with rxd
sample delay logic (SSI_HAS_RX_SAMPLE_DELAY==1). When the DW_apb_ssi is
not configured with rxd sample delay logic, this register will not exist
and writing to its address location will have no effect; reading from
its address will return zero. This register control the number of ssi_clk
cycles that are delayed (from the default sample time) before the actual
sample of the rxd input occurs. It is impossible to write to this
register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and
disabled by writing to the SSIENR register.
msticr 0x44 32 RO 0x0 
Multi-Master Interrupt Clear Register
rsvd_0 0xF4 32 RO 0x0 
RSVD_0 - Reserved address location
rsvd_1 0xF8 32 RO 0x0 
RSVD_1 - Reserved address location
rsvd_2 0xFC 32 RO 0x0 
RSVD_2 - Reserved address location