ctrlr0

         Control Register 0:
This register controls the serial data transfer. It is impossible to
write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
is enabled and disabled by writing to the SSIENR register.
      
Module Instance Base Address Register Address
i_spim_0_spim 0xFFDA4000 0xFFDA4000
i_spim_1_spim 0xFFDA5000 0xFFDA5000

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfs

RW 0x0

srl

RW 0x0

Reserved

tmod

RW 0x0

scpol

RW 0x0

scph

RW 0x0

frf

RW 0x0

dfs

RW 0x7

ctrlr0 Fields

Bit Name Description Access Reset
15:12 cfs
Control Frame Size. Selects the length of the control word for the
Microwire frame format
Value Description
0xa SIZE11BIT
0xb SIZE12BIT
0xc SIZE13BIT
0xd SIZE14BIT
0xe SIZE15BIT
0xf SIZE16BIT
0x0 SIZE1BIT
0x1 SIZE2BIT
0x2 SIZE3BIT
0x3 SIZE4BIT
0x4 SIZE5BIT
0x05 SIZE6BIT
0x6 SIZE7BIT
0x7 SIZE8BIT
0x8 SIZE9BIT
0x9 SIZE10BIT
RW 0x0
11 srl
Shift Register Loop. Used for testing purposes only. When internally
active, connects the transmit shift register output to the receive
shift register input.
0 - Normal Mode Operation
1 - Test Mode Operation
Value Description
0x0 NORMMODE
0x1 TESTMODE
RW 0x0
9:8 tmod
Transfer Mode.
Selects the mode of transfer for serial communication. This field does
not affect the transfer duplicity. Only indicates whether the receive or
transmit data are valid. In transmit-only mode, data received from the
external device is not valid and is not stored in the receive FIFO memory;
it is overwritten on the next transfer. In receive-only mode, transmitted
data are not valid. After the first write to the transmit FIFO, the same
word is retransmitted for the duration of the transfer. In
transmit-and-receive mode, both transmit and receive data are valid.
The transfer continues until the transmit FIFO is empty. Data received
from the external device are stored into the receive FIFO memory, where
it can be accessed by the host processor.
00 - Transmit & Receive
01 - Transmit Only
10 - Receive Only
11 - Reserved
Value Description
0x0 TXRX
0x1 TXONLY
0x2 RXONLY
0x3 EERD
RW 0x0
7 scpol
Serial Clock Polarity.
Valid when the frame format (FRF) is set to Motorola SPI. Used to select
the polarity of the inactive serial clock, which is held inactive when
the DW_apb_ssi master is not actively transferring data on the serial bus.
0 - Inactive state of serial clock is low
1 - Inactive state of serial clock is high
Value Description
0x0 INACTIVELOW
0x1 INACTIVEHIGH
RW 0x0
6 scph
Serial Clock Phase.
Valid when the frame format (FRF) is set to Motorola SPI. The serial
clock phase selects the relationship of the serial clock with the slave
select signal. When SCPH = 0, data are captured on the first edge of
the serial clock. When SCPH = 1, the serial clock starts toggling one
cycle after the slave select line is activated, and data are captured
on the second edge of the serial clock.
0: Serial clock toggles in middle of first data bit
1: Serial clock toggles at start of first data bit
Value Description
0x0 MIDBIT
0x1 STARTBIT
RW 0x0
5:4 frf
Frame Format.
Selects which serial protocol transfers the data.
00 - Motorola SPI
01 - Texas Instruments SSP
10 - National Semiconductors Microwire
11 - Reserved
Value Description
0x0 MOTSPI
0x1 TISSP
0x2 NATMW
RW 0x0
3:0 dfs
Data Frame Size.
Selects the data frame length. When the data frame size is programmed
to be less than 16 bits, the receive data are automatically
right-justified by the receive logic, with the upper bits of the receive
FIFO zero-padded. You must right-justify transmit data before writing
into the transmit FIFO. The transmit logic ignores the upper unused
bits when transmitting the data
Value Description
0xa WIDTH11BIT
0xb WIDTH12BIT
0xc WIDTH13BIT
0xd WIDTH14BIT
0xe WIDTH15BIT
0xf WIDTH16BIT
0x3 WIDTH4BIT
0x4 WIDTH5BIT
0x5 WIDTH6BIT
0x6 WIDTH7BIT
0x7 WIDTH8BIT
0x8 WIDTH9BIT
0x9 WIDTH10BIT
RW 0x7