msticr
Multi-Master Interrupt Clear Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spim_0_spim | 0xFFDA4000 | 0xFFDA4044 |
| i_spim_1_spim | 0xFFDA5000 | 0xFFDA5044 |
Offset: 0x44
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
msticr RO 0x0 |
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msticr Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | msticr | Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect. |
RO | 0x0 |