rx_sample_dly

         RX Sample Delay.
This register controls the number of ssi_clk
cycles that are delayed (from the default sample time) before 
the actual sample of the rxd input occurs. It is impossible to 
write to this register when the SPI master is enabled. The SPI 
master is enabled and disabled by writing to the SSIENR register.

Module Instance	Base Address	Register Address
`i_spim_0_spim`	`0xFFDA4000`	`0xFFDA40F0`
`i_spim_1_spim`	`0xFFDA5000`	`0xFFDA50F0`

Offset: 0xF0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`rsd` `RW 0x0`

rx_sample_dly Fields

Bit	Name	Description	Access	Reset
7:0	`rsd`	Rxd Sample Delay. This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. NOTE: You must program the rsd field to 0x1 or greater for correct operation. In addition, if you program this register to a value that exceeds the depth of the internal shift registers (SSI_RX_DLY_SR_DEPTH), zero delay is applied to the rxd sample and the interface does not function correctly.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

7:0

rsd

Rxd Sample Delay.
This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. 
NOTE: You must program the rsd field to 0x1 or greater for correct operation.  
In addition, if you program this register to a value that exceeds the depth of the internal shift registers (SSI_RX_DLY_SR_DEPTH), 
zero delay is applied to the rxd sample and the interface does not function correctly.

RW

0x0