dmardlr

         DMA Receive Data Level.
This register is only valid when DW_apb_ssi is configured with a set of
DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
for DMA operation, this register will not exist and writing to its address
will have no effect; reading from its address will return zero.
Module Instance Base Address Register Address
i_spim_0_spim 0xFFDA4000 0xFFDA4054
i_spim_1_spim 0xFFDA5000 0xFFDA5054

Offset: 0x54

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dmardl

RW 0x0

dmardlr Fields

Bit Name Description Access Reset
7:0 dmardl 
Receive Data Level.
This bit field controls the level at which a DMA request is made by the
receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
generated when the number of valid data entries in the receive FIFO is
equal to or above this field value + 1, and RDMAE=1.
 RW 0x0