rxoicr

         Receive FIFO Overflow Interrupt Clear Register

Module Instance	Base Address	Register Address
`i_spim_0_spim`	`0xFFDA4000`	`0xFFDA403C`
`i_spim_1_spim`	`0xFFDA5000`	`0xFFDA503C`

Offset: 0x3C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`rxoicr` `RO 0x0`

rxoicr Fields

Bit	Name	Description	Access	Reset
0	`rxoicr`	Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxo_intr interrupt; writing has no effect.	`RO`	`0x0`