i2c Address Map

Module Instance	Base Address	End Address
`i_i2c_0_i2c`	`0xFFC02200`	`0xFFC022FF`
`i_i2c_1_i2c`	`0xFFC02300`	`0xFFC023FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`ic_con`	`0x0`	`32`	`RW`	`0x7D`	I2C Control Register
`ic_tar`	`0x4`	`32`	`RW`	`0x1055`	I2C Target Address Register
`ic_sar`	`0x8`	`32`	`RW`	`0x55`	I2C Slave Address Register
`ic_data_cmd`	`0x10`	`32`	`RW`	`0x0`	I2C Rx/Tx Data Buffer and Command Register
`ic_ss_scl_hcnt`	`0x14`	`32`	`RW`	`0x190`	Standard Speed I2C Clock SCL High Count Register
`ic_ss_scl_lcnt`	`0x18`	`32`	`RW`	`0x1D6`	Standard Speed I2C Clock SCL Low Count Register
`ic_fs_scl_hcnt`	`0x1C`	`32`	`RW`	`0x3C`	Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
`ic_fs_scl_lcnt`	`0x20`	`32`	`RW`	`0x82`	Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
`ic_intr_stat`	`0x2C`	`32`	`RO`	`0x0`	I2C Interrupt Status Register
`ic_intr_mask`	`0x30`	`32`	`RW`	`0x8FF`	I2C Interrupt Mask Register
`ic_raw_intr_stat`	`0x34`	`32`	`RO`	`0x0`	I2C Raw Interrupt Status Register
`ic_rx_tl`	`0x38`	`32`	`RW`	`0x0`	I2C Receive FIFO Threshold Register
`ic_tx_tl`	`0x3C`	`32`	`RW`	`0x0`	I2C Transmit FIFO Threshold Register
`ic_clr_intr`	`0x40`	`32`	`RO`	`0x0`	Clear Combined and Individual Interrupt Register
`ic_clr_rx_under`	`0x44`	`32`	`RO`	`0x0`	Clear RX_UNDER Interrupt Register
`ic_clr_rx_over`	`0x48`	`32`	`RO`	`0x0`	Clear RX_OVER Interrupt Register
`ic_clr_tx_over`	`0x4C`	`32`	`RO`	`0x0`	Clear TX_OVER Interrupt Register
`ic_clr_rd_req`	`0x50`	`32`	`RO`	`0x0`	Clear RD_REQ Interrupt Register
`ic_clr_tx_abrt`	`0x54`	`32`	`RO`	`0x0`	Clear TX_ABRT Interrupt Register
`ic_clr_rx_done`	`0x58`	`32`	`RO`	`0x0`	Clear RX_DONE Interrupt Register
`ic_clr_activity`	`0x5C`	`32`	`RO`	`0x0`	Clear ACTIVITY Interrupt Register
`ic_clr_stop_det`	`0x60`	`32`	`RO`	`0x0`	Clear STOP_DET Interrupt Register
`ic_clr_start_det`	`0x64`	`32`	`RO`	`0x0`	Clear START_DET Interrupt Register
`ic_clr_gen_call`	`0x68`	`32`	`RO`	`0x0`	Clear GEN_CALL Interrupt Register
`ic_enable`	`0x6C`	`32`	`RW`	`0x0`	I2C Enable Register
`ic_status`	`0x70`	`32`	`RO`	`0x6`	I2C Status Register
`ic_txflr`	`0x74`	`32`	`RO`	`0x0`	I2C Transmit FIFO Level Register
`ic_rxflr`	`0x78`	`32`	`RO`	`0x0`	I2C Receive FIFO Level Register
`ic_sda_hold`	`0x7C`	`32`	`RW`	`0x1`	I2C SDA Hold Time Length Register
`ic_tx_abrt_source`	`0x80`	`32`	`RO`	`0x0`	I2C Transmit Abort Source Register
`ic_slv_data_nack_only`	`0x84`	`32`	`RW`	`0x0`	Generate Slave Data NACK Register.
`ic_dma_cr`	`0x88`	`32`	`RW`	`0x0`	DMA Control Register
`ic_dma_tdlr`	`0x8C`	`32`	`RW`	`0x0`	DMA Transmit Data Level Register
`ic_dma_rdlr`	`0x90`	`32`	`RW`	`0x0`	I2C Receive Data Level Register
`ic_sda_setup`	`0x94`	`32`	`RW`	`0x64`	I2C SDA Setup Register
`ic_ack_general_call`	`0x98`	`32`	`RW`	`0x1`	I2C ACK General Call Register
`ic_enable_status`	`0x9C`	`32`	`RO`	`0x0`	I2C Enable Status Register
`ic_comp_param_1`	`0xF4`	`32`	`RO`	`0x3F3FEA`	Component Parameter Register 1
`ic_comp_version`	`0xF8`	`32`	`RO`	`0x3132312A`	I2C Component Version Register
`ic_comp_type`	`0xFC`	`32`	`RO`	`0x44570140`	I2C Component Type Register
`ic_fs_spklen`	`0xA0`	`32`	`RW`	`0x2`	I2C SS, FS or FM+ spike suppression limit
`ic_clr_restart_det`	`0xA8`	`32`	`RO`	`0x0`	Clear RESTART_DET Interrupt Register