ic_dma_tdlr

         DMA Transmit Data Level Register

Module Instance	Base Address	Register Address
`i_i2c_0_i2c`	`0xFFC02200`	`0xFFC0228C`
`i_i2c_1_i2c`	`0xFFC02300`	`0xFFC0238C`

Offset: 0x8C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`dmatdl` `RW 0x0`

ic_dma_tdlr Fields

Bit	Name	Description	Access	Reset
5:0	`dmatdl`	Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0	`RW`	`0x0`

Bit

Name

Description

Access

Reset

5:0

dmatdl

Transmit Data Level.
This bit field controls the level at which a
DMA request is made by the transmit logic. It
is equal to the watermark level; that is, the
dma_tx_req signal is generated when the number
of valid data entries in the transmit FIFO is
equal to or below this field value, and TDMAE = 1.
Reset value: 0x0

RW

0x0