ic_tar

         Name: I2C Target Address Register

All bits can be dynamically updated as long as any set of the following
conditions are true:
- The I2C is NOT enabled (IC_ENABLE[0] is set to 0);
   or
- The I2C is enabled (IC_ENABLE[0]=1);
   AND
  the I2C is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0);
   AND
  I2C is enabled to operate in Master mode (IC_CON[0]=1);
   AND
  there are NO entries in the TX FIFO (IC_STATUS[2]=1)

Module Instance	Base Address	Register Address
`i_i2c_0_i2c`	`0xFFC02200`	`0xFFC02204`
`i_i2c_1_i2c`	`0xFFC02300`	`0xFFC02304`

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`ic_10bitaddr_master` `RW 0x1`	`special` `RW 0x0`	`gc_or_start` `RW 0x0`	`ic_tar` `RW 0x55`

ic_tar Fields

Bit

Name

Description

Access

Reset

ic_10bitaddr_master

This bit controls whether the I2C starts its transfers in 7-
or 10-bit addressing mode when acting as a master.
0: 7-bit addressing
1: 10-bit addressing

Reset value: 0x1

Value	Description
0x0	START7
0x1	START10

RW

0x1

special

This bit indicates whether software performs a General Call or
START BYTE command.
0: ignore bit 10 GC_OR_START and use IC_TAR normally
1: perform special I2C command as specified in GC_OR_START
   bit
Reset value: 0x0

Value	Description
0x0	GENCALL
0x1	STARTBYTE

RW

0x0

gc_or_start

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a
General Call or START byte command is to be performed by the
I2C.
0: General Call Address  after issuing a General Call, only writes
   may be performed. Attempting to issue a read command results in
   setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
   The I2C remains in General Call mode until the
   SPECIAL bit value (bit 11) is cleared.
1: START BYTE
Reset value: 0x0

Value	Description
0x0	GENCALL
0x1	STARTBYTE

RW

0x0

9:0

ic_tar

This is the target address for any master transaction. When
transmitting a General Call, these bits are ignored. To generate a
START BYTE, the CPU needs to write only once into these bits.
Reset value: 0x55
If the IC_TAR and IC_SAR are the same, loopback exists but the
FIFOs are shared between master and slave, so full loopback is
not feasible. Only one direction loopback mode is supported
(simplex), not duplex. A master cannot transmit to itself; it can
transmit to only a slave.

RW

0x55