ic_sda_setup

         I2C SDA Setup Register

This register controls the amount of time delay
(in terms of number of l4_sp_clk clock periods) introduced
in the rising edge of SCL, relative to SDA changing, when
the I2C module services a read request in a slave-transmitter operation.
The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
I2C Bus Specification.
Module Instance Base Address Register Address
i_i2c_0_i2c 0xFFC02200 0xFFC02294
i_i2c_1_i2c 0xFFC02300 0xFFC02394

Offset: 0x94

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sda_setup

RW 0x64

ic_sda_setup Fields

Bit Name Description Access Reset
7:0 sda_setup 
SDA Setup.
It is recommended that if the required delay is 1000ns,
then for an l4_sp_clk frequency of 10 MHz, IC_SDA_SETUP
should be programmed to a value of 11.
Default Reset value: 0x64
 RW 0x64