ic_fs_scl_hcnt

         Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
      
Module Instance Base Address Register Address
i_i2c_0_i2c 0xFFC02200 0xFFC0221C
i_i2c_1_i2c 0xFFC02300 0xFFC0231C

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ic_fs_scl_hcnt

RW 0x3C

ic_fs_scl_hcnt Fields

Bit Name Description Access Reset
15:0 ic_fs_scl_hcnt
This register must be set before any I2C bus transaction can take place to
ensure proper I/O timing. This register sets the SCL clock high-period
count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code
and START BYTE or General CALL. 
This register can be written only
when the I2C interface is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.
The minimum valid value is 6; hardware prevents values less than this
being written, and if attempted results in 6 being set.

Reset value: 0x003C
RW 0x3C