i2c Summary

Module Instance	Base Address
`i_i2c_0_i2c`	`0xFFC02200`
`i_i2c_1_i2c`	`0xFFC02300`

Register Address Offset	Bit Fields
`i_i2c_0_i2c`
`ic_con` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_con_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_con_31to9` `RO 0x0`							`tx_empty_ctrl` `RW 0x0`	`stop_det_ifaddressed` `RW 0x0`	`ic_slave_disable` `RW 0x1`	`ic_restart_en` `RW 0x1`	`ic_10bitaddr_master` `RO 0x1`	`ic_10bitaddr_slave` `RW 0x1`	`speed` `RW 0x2`		`master_mode` `RW 0x1`
`ic_tar` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`ic_10bitaddr_master` `RW 0x1`	`special` `RW 0x0`	`gc_or_start` `RW 0x0`	`ic_tar` `RW 0x55`
`ic_sar` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`ic_sar` `RW 0x55`
`ic_data_cmd` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`					`restart` `WO 0x0`	`stop` `WO 0x0`	`cmd` `WO 0x0`	`dat` `RW 0x0`
`ic_ss_scl_hcnt` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_ss_scl_hcnt` `RW 0x190`
`ic_ss_scl_lcnt` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_ss_scl_lcnt` `RW 0x1D6`
`ic_fs_scl_hcnt` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_fs_scl_hcnt` `RW 0x3C`
`ic_fs_scl_lcnt` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_fs_scl_lcnt` `RW 0x82`
`ic_intr_stat` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`r_master_on_hold` `RO 0x0`	`r_restart_det` `RO 0x0`	`r_gen_call` `RO 0x0`	`r_start_det` `RO 0x0`	`r_stop_det` `RO 0x0`	`r_activity` `RO 0x0`	`r_rx_done` `RO 0x0`	`r_tx_abrt` `RO 0x0`	`r_rd_req` `RO 0x0`	`r_tx_empty` `RO 0x0`	`r_tx_over` `RO 0x0`	`r_rx_full` `RO 0x0`	`r_rx_over` `RO 0x0`	`r_rx_under` `RO 0x0`
`ic_intr_mask` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`m_master_on_hold` `RW 0x0`	`m_restart_det` `RW 0x0`	`m_gen_call` `RW 0x1`	`m_start_det` `RW 0x0`	`m_stop_det` `RW 0x0`	`m_activity` `RW 0x0`	`m_rx_done` `RW 0x1`	`m_tx_abrt` `RW 0x1`	`m_rd_req` `RW 0x1`	`m_tx_empty` `RW 0x1`	`m_tx_over` `RW 0x1`	`m_rx_full` `RW 0x1`	`m_rx_over` `RW 0x1`	`m_rx_under` `RW 0x1`
`ic_raw_intr_stat` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`master_on_hold` `RO 0x0`	`restart_det` `RO 0x0`	`gen_call` `RO 0x0`	`start_det` `RO 0x0`	`stop_det` `RO 0x0`	`activity` `RO 0x0`	`rx_done` `RO 0x0`	`tx_abrt` `RO 0x0`	`rd_req` `RO 0x0`	`tx_empty` `RO 0x0`	`tx_over` `RO 0x0`	`rx_full` `RO 0x0`	`rx_over` `RO 0x0`	`rx_under` `RO 0x0`
`ic_rx_tl` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rx_tl` `RW 0x0`
`ic_tx_tl` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`tx_tl` `RW 0x0`
`ic_clr_intr` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_intr` `RO 0x0`
`ic_clr_rx_under` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_under` `RO 0x0`
`ic_clr_rx_over` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_over` `RO 0x0`
`ic_clr_tx_over` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_tx_over` `RO 0x0`
`ic_clr_rd_req` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rd_req` `RO 0x0`
`ic_clr_tx_abrt` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_tx_abort` `RO 0x0`
`ic_clr_rx_done` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_done` `RO 0x0`
`ic_clr_activity` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_activity` `RO 0x0`
`ic_clr_stop_det` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_stop_det` `RO 0x0`
`ic_clr_start_det` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_start_det` `RO 0x0`
`ic_clr_gen_call` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_gen_call` `RO 0x0`
`ic_enable` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`txabort` `RW 0x0`	`enable` `RW 0x0`
`ic_status` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`slv_activity` `RO 0x0`	`mst_activity` `RO 0x0`	`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`activity` `RO 0x0`
`ic_txflr` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`txflr` `RO 0x0`
`ic_rxflr` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`rxflr` `RO 0x0`
`ic_sda_hold` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`ic_sda_rx_hold` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_sda_tx_hold` `RW 0x1`
`ic_tx_abrt_source` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tx_flush_cnt` `RO 0x0`									`rsvd_ic_tx_abrt_source_22to17` `RO 0x0`						`abrt_user_abrt` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`abrt_slvrd_intx` `RO 0x0`	`abrt_slv_arblost` `RO 0x0`	`abrt_slvflush_txfifo` `RO 0x0`	`arb_lost` `RO 0x0`	`abrt_master_dis` `RO 0x0`	`abrt_10b_rd_norstrt` `RO 0x0`	`abrt_sbyte_norstrt` `RO 0x0`	`abrt_hs_norstrt` `RO 0x0`	`abrt_sbyte_ackdet` `RO 0x0`	`abrt_hs_ackdet` `RO 0x0`	`abrt_gcall_read` `RO 0x0`	`abrt_gcall_noack` `RO 0x0`	`abrt_txdata_noack` `RO 0x0`	`abrt_10addr2_noack` `RO 0x0`	`abrt_10addr1_noack` `RO 0x0`	`abrt_7b_addr_noack` `RO 0x0`
`ic_slv_data_nack_only` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`nack` `RW 0x0`
`ic_dma_cr` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_dma_cr_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_dma_cr_31to2` `RO 0x0`														`tdmae` `RW 0x0`	`rdmae` `RW 0x0`
`ic_dma_tdlr` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`dmatdl` `RW 0x0`
`ic_dma_rdlr` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`dmardl` `RW 0x0`
`ic_sda_setup` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`sda_setup` `RW 0x64`
`ic_ack_general_call` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_ack_gen_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_ack_gen_31to1` `RO 0x0`															`ack_gen_call` `RW 0x1`
`ic_enable_status` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`slv_rx_data_lost` `RO 0x0`	`slv_disabled_while_busy` `RO 0x0`	`ic_en` `RO 0x0`
`ic_comp_param_1` `0xF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`tx_buffer_depth` `RO 0x3F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rx_buffer_depth` `RO 0x3F`								`add_encoded_params` `RO 0x1`	`has_dma` `RO 0x1`	`intr_io` `RO 0x1`	`hc_count_values` `RO 0x0`	`max_speed_mode` `RO 0x2`		`apb_data_width` `RO 0x2`
`ic_comp_version` `0xF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ic_comp_version` `RO 0x3132312A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_comp_version` `RO 0x3132312A`
`ic_comp_type` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ic_comp_type` `RO 0x44570140`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_comp_type` `RO 0x44570140`
`ic_fs_spklen` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`ic_fs_spklen` `RW 0x2`
`ic_clr_restart_det` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_restart_det` `RO 0x0`
`i_i2c_1_i2c`
`ic_con` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_con_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_con_31to10` `RO 0x0`						`rx_fifo_full_hld_ctrl` `RW 0x0`	`tx_empty_ctrl` `RW 0x0`	`stop_det_ifaddressed` `RW 0x0`	`ic_slave_disable` `RW 0x1`	`ic_restart_en` `RW 0x1`	`ic_10bitaddr_master` `RO 0x1`	`ic_10bitaddr_slave` `RW 0x1`	`speed` `RW 0x2`		`master_mode` `RW 0x1`
`ic_tar` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`ic_10bitaddr_master` `RW 0x1`	`special` `RW 0x0`	`gc_or_start` `RW 0x0`	`ic_tar` `RW 0x55`
`ic_sar` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`ic_sar` `RW 0x55`
`ic_data_cmd` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`					`restart` `WO 0x0`	`stop` `WO 0x0`	`cmd` `WO 0x0`	`dat` `RW 0x0`
`ic_ss_scl_hcnt` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_ss_scl_hcnt` `RW 0x190`
`ic_ss_scl_lcnt` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_ss_scl_lcnt` `RW 0x1D6`
`ic_fs_scl_hcnt` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_fs_scl_hcnt` `RW 0x3C`
`ic_fs_scl_lcnt` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_fs_scl_lcnt` `RW 0x82`
`ic_intr_stat` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`r_master_on_hold` `RO 0x0`	`r_restart_det` `RO 0x0`	`r_gen_call` `RO 0x0`	`r_start_det` `RO 0x0`	`r_stop_det` `RO 0x0`	`r_activity` `RO 0x0`	`r_rx_done` `RO 0x0`	`r_tx_abrt` `RO 0x0`	`r_rd_req` `RO 0x0`	`r_tx_empty` `RO 0x0`	`r_tx_over` `RO 0x0`	`r_rx_full` `RO 0x0`	`r_rx_over` `RO 0x0`	`r_rx_under` `RO 0x0`
`ic_intr_mask` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`m_master_on_hold` `RW 0x0`	`m_restart_det` `RW 0x0`	`m_gen_call` `RW 0x1`	`m_start_det` `RW 0x0`	`m_stop_det` `RW 0x0`	`m_activity` `RW 0x0`	`m_rx_done` `RW 0x1`	`m_tx_abrt` `RW 0x1`	`m_rd_req` `RW 0x1`	`m_tx_empty` `RW 0x1`	`m_tx_over` `RW 0x1`	`m_rx_full` `RW 0x1`	`m_rx_over` `RW 0x1`	`m_rx_under` `RW 0x1`
`ic_raw_intr_stat` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`master_on_hold` `RO 0x0`	`restart_det` `RO 0x0`	`gen_call` `RO 0x0`	`start_det` `RO 0x0`	`stop_det` `RO 0x0`	`activity` `RO 0x0`	`rx_done` `RO 0x0`	`tx_abrt` `RO 0x0`	`rd_req` `RO 0x0`	`tx_empty` `RO 0x0`	`tx_over` `RO 0x0`	`rx_full` `RO 0x0`	`rx_over` `RO 0x0`	`rx_under` `RO 0x0`
`ic_rx_tl` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rx_tl` `RW 0x0`
`ic_tx_tl` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`tx_tl` `RW 0x0`
`ic_clr_intr` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_intr` `RO 0x0`
`ic_clr_rx_under` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_under` `RO 0x0`
`ic_clr_rx_over` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_over` `RO 0x0`
`ic_clr_tx_over` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_tx_over` `RO 0x0`
`ic_clr_rd_req` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rd_req` `RO 0x0`
`ic_clr_tx_abrt` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_tx_abort` `RO 0x0`
`ic_clr_rx_done` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_rx_done` `RO 0x0`
`ic_clr_activity` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_activity` `RO 0x0`
`ic_clr_stop_det` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_stop_det` `RO 0x0`
`ic_clr_start_det` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_start_det` `RO 0x0`
`ic_clr_gen_call` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_gen_call` `RO 0x0`
`ic_enable` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`txabort` `RW 0x0`	`enable` `RW 0x0`
`ic_status` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`slv_activity` `RO 0x0`	`mst_activity` `RO 0x0`	`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`activity` `RO 0x0`
`ic_txflr` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`txflr` `RO 0x0`
`ic_rxflr` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`rxflr` `RO 0x0`
`ic_sda_hold` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`ic_sda_rx_hold` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_sda_tx_hold` `RW 0x1`
`ic_tx_abrt_source` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tx_flush_cnt` `RO 0x0`									`rsvd_ic_tx_abrt_source_22to17` `RO 0x0`						`abrt_user_abrt` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`abrt_slvrd_intx` `RO 0x0`	`abrt_slv_arblost` `RO 0x0`	`abrt_slvflush_txfifo` `RO 0x0`	`arb_lost` `RO 0x0`	`abrt_master_dis` `RO 0x0`	`abrt_10b_rd_norstrt` `RO 0x0`	`abrt_sbyte_norstrt` `RO 0x0`	`abrt_hs_norstrt` `RO 0x0`	`abrt_sbyte_ackdet` `RO 0x0`	`abrt_hs_ackdet` `RO 0x0`	`abrt_gcall_read` `RO 0x0`	`abrt_gcall_noack` `RO 0x0`	`abrt_txdata_noack` `RO 0x0`	`abrt_10addr2_noack` `RO 0x0`	`abrt_10addr1_noack` `RO 0x0`	`abrt_7b_addr_noack` `RO 0x0`
`ic_slv_data_nack_only` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`nack` `RW 0x0`
`ic_dma_cr` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_dma_cr_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_dma_cr_31to2` `RO 0x0`														`tdmae` `RW 0x0`	`rdmae` `RW 0x0`
`ic_dma_tdlr` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`dmatdl` `RW 0x0`
`ic_dma_rdlr` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`dmardl` `RW 0x0`
`ic_sda_setup` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`sda_setup` `RW 0x64`
`ic_ack_general_call` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ic_ack_gen_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ic_ack_gen_31to1` `RO 0x0`															`ack_gen_call` `RW 0x1`
`ic_enable_status` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`slv_rx_data_lost` `RO 0x0`	`slv_disabled_while_busy` `RO 0x0`	`ic_en` `RO 0x0`
`ic_comp_param_1` `0xF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`tx_buffer_depth` `RO 0x3F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rx_buffer_depth` `RO 0x3F`								`add_encoded_params` `RO 0x1`	`has_dma` `RO 0x1`	`intr_io` `RO 0x1`	`hc_count_values` `RO 0x0`	`max_speed_mode` `RO 0x2`		`apb_data_width` `RO 0x2`
`ic_comp_version` `0xF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ic_comp_version` `RO 0x3132312A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_comp_version` `RO 0x3132312A`
`ic_comp_type` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ic_comp_type` `RO 0x44570140`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ic_comp_type` `RO 0x44570140`
`ic_fs_spklen` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`ic_fs_spklen` `RW 0x2`
`ic_clr_restart_det` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`clr_restart_det` `RO 0x0`