MainPll_grp Address Map

Contains registers with settings for the Main PLL.
Module Instance Base Address End Address
i_clk_mgr_mainpllgrp 0xFFD10024 0xFFD1007B
Register Offset Width Access Reset Value Description
en 0x0 32 RW 0x000000FF 
Enable Register
ens 0x4 32 RW 0x00000080 
Enable Set Register
enr 0x8 32 RW 0x00000080 
Enable Reset Register
bypass 0xC 32 RW 0x0000003F 
Bypass Register
bypasss 0x10 32 RW 0x0000003F 
Bypass Set Register
bypassr 0x14 32 RW 0x0000003F 
Bypass Reset Register
mpuclk 0x18 32 RW 0x00000000 
Main PLL Control Register for MPU Clock Group.
nocclk 0x1C 32 RW 0x00010000 
Main PLL Control Register for NOC Clock Group.
nocdiv 0x20 32 RW 0x10020100 
NoC Divide Register
pllglob 0x24 32 RW 0x15000101 
This refects register settings for all the channels of the main PLL
fdbck 0x28 32 RW 0x2A000000 
VCO freq register counters
mem 0x2C 32 RW 0x00000000 
Registers dealing with PLL internal memory access.
memstat 0x30 32 RW 0x00000000 
Main PLL memstatus register. contains memory read data
pllc0 0x34 32 RW 0x00000003 
Channel C0 frequency settings for the main PLL
pllc1 0x38 32 RW 0x10000008 
Channel C1 frequency settings for the main PLL
vcocalib 0x3C 32 RW 0x00010874 
VCO calibration control registers.
pllc2 0x40 32 RW 0x00000006 
Channel C2 frequency settings for the main PLL
pllc3 0x44 32 RW 0x1000000F 
Channel C3 frequency settings for the main PLL
pllm 0x48 32 RW 0x00000078 
Feedback Clock Divider Control (VCO Frequency Register Counters)
fhop 0x4C 32 RW 0x00000000 
Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register.
ssc 0x50 32 RO 0x00000000 
Spread Spectrum Clocking (SSC) Control and Status Registers.
lostlock 0x54 32 RW 0x00000000