pllm

         Feedback Clock Divider Control (VCO Frequency Register Counters)
      
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD10024 0xFFD1006C

Size: 32

Offset: 0x48

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mdiv

RW 0x78

pllm Fields

Bit Name Description Access Reset
9:0 mdiv
Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state. 
It cannot be switched dynamically.
RW 0x78