ssc
Spread Spectrum Clocking (SSC) Control and Status Registers.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_clk_mgr_mainpllgrp | 0xFFD10024 | 0xFFD10074 |
Size: 32
Offset: 0x50
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
stat RO 0x0 |
Reserved |
en RW 0x0 |
||||||||||||
ssc Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 8 | stat |
Indicates whether SSC is running. 1—SSC is active/enabled. Will only go to 1 once ictl_pll_freqgen_ssc_en_a has been asserted to 1. HP PLL output is at a SSC frequency. 0—SSC is disabled and that the HP PLL output frequency has returned to nominal frequency.
|
RO | 0x0 | ||||||
| 0 | en |
Enables/Disables SSC. 1—SSC is enabled (HP PLL output is running at spread spectrum mode) 0—SSC is disabled (HP PLL output will be at the nominal frequency)
|
RW | 0x0 |