bypassr

         Write One to Clear corresponding fields in Bypass Register.

Module Instance	Base Address	Register Address
`i_clk_mgr_mainpllgrp`	`0xFFD10024`	`0xFFD10038`

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`													`s2fuser0` `RW 0x1`	`noc` `RW 0x1`	`mpu` `RW 0x1`

bypassr Fields

Bit	Name	Description	Access	Reset
2	`s2fuser0`	If set, the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL.	`RW`	`0x1`
1	`noc`	If set, the NOC clock group will be bypassed to the input clock reference of the Main PLL.	`RW`	`0x1`
0	`mpu`	If set, the MPU clock group will be bypassed to the input clock reference of the Main PLL.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

s2fuser0

If set, the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL.

RW

0x1

noc

If set, the NOC clock group will be bypassed to the input clock reference of the Main PLL.

RW

0x1

mpu

If set, the MPU clock group will be bypassed to the input clock reference of the Main PLL.

RW

0x1