enr 

         Write One to Clear corresponding fields in Enable Register.
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD10024 0xFFD1002C

Size: 32

Offset: 0x8

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

s2fuser0clken

RW 0x0

cstimerclken

RW 0x0

csclken

RW 0x0

l4spclken

RW 0x0

l4mpclken

RW 0x0

l4mainclken

RW 0x0

mpuclken

RW 0x0

enr Fields

Bit Name Description Access Reset
6 s2fuser0clken 
Enables clock s2f_user0_clk output
 RW 0x0
5 cstimerclken 
Enables Debug Timer Clock output (cs_timer_clk)
 RW 0x0
4 csclken 
Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)
 RW 0x0
3 l4spclken 
Enables clock l4_sp_clk output
 RW 0x0
2 l4mpclken 
Enables clock l4_mp_clk output
 RW 0x0
1 l4mainclken 
Enables clock l4_main_clk output
 RW 0x0
0 mpuclken 
Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
 RW 0x0