lostlock

Module Instance	Base Address	Register Address
`i_clk_mgr_mainpllgrp`	`0xFFD10024`	`0xFFD10078`

Size: 32

Offset: 0x54

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`bypass_cleared` `RW 0x0`

lostlock Fields

Bit	Name	Description	Access	Reset
0	`bypass_cleared`	When all the bypass_en asserted due to loss of PLL lock from all the channels go low this bit gets set to 1. This is should clear clr_lostlock_bypass automatically. Before setting clr_lostlock_bypass, SW should clear this register.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

bypass_cleared

When all the bypass_en asserted due to loss of PLL  lock from all the channels go low this bit gets set to 1. 

This is should clear clr_lostlock_bypass automatically. Before setting clr_lostlock_bypass, SW should clear this register.

RW

0x0