External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 4/24/2025
Public
Document Table of Contents

4.1.3. Functional Simulation with Verilog HDL

Simulation scripts for the Synopsys* , Cadence, and Siemens EDA simulators are provided for you to run the design example.

Simulation scripts in the simulation folders for design example are located as follows:

  • sim\ed_sim\mentor\msim_setup.tcl
  • sim\ed_sim\synopsys\vcsmx\vcsmx_setup.sh
  • sim\ed_sim\xcelium\xcelium_setup.sh

For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Questa - Intel FPGA Edition, ModelSim, and QuestaSim Simulator Support chapter in the Quartus® Prime Pro Edition User Guide, Third-party Simulation.