External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 4/24/2025
Public
Document Table of Contents

6.7. Debugging with the External Memory Interface Debug Toolkit

The External Memory Interface Debug Toolkit for Agilex™ 3 FPGAs provides access to data collected by the sequencer during memory calibration, as well as analysis tools to evaluate the stability of the calibrated interface and assess hardware conditions.
Note: Because the HPS EMIF controller does not support the External Memory Interface Debug Toolkit, verify that the HPS memory interface is operational using the non-HPS memory controller first. Create a design that instantiates the FPGA memory controller, use parameters that will be used for the HPS memory interface, and route it to the same I/O that the HPS EMIF uses.

The debug toolkit provides the following types of reports:

  • Interface and memory configuration, such as external memory protocol and interface width.
  • Calibration results, including calibration status (pass or fail), calibration failure stage (if applicable), delay settings and margins, and VREF settings and margins.

The available task and analysis capabilities include the following:

  • Ability to request recalibration of the memory interface.
  • Ability to run the test engine in the design example.
  • Ability to view the delay setting on any pin in the selected interface and update it if necessary.
  • Ability to run VREF margining on the interface.
  • Ability to run driver margining on the interface.