External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 847458
Date 4/24/2025
Public
Document Table of Contents

6.11.3.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox

This example provides instructions for sending recalibration request and reading the calibration status using the mailbox.

The values in this example are for illustrative purposes and are obtained from an EMIF example design usingLPDDR4 2CH x16.

In a 2CH x16 LPDDR4 design, CH0 uses the Primary MC while the CH1 uses the secondary MC in the IO96 Bank; hence the CMD_TARGET_IP_TYPE is 0x1 for CH0 , and 0x2 for CH1. The CMD_TARGET_IP_INSTANCE defaults to 0 in the example design generated by the Quartus® Prime software.

The table below illustrates the construction of the data to be written to the CMD_REQ register for this request:

Channel CMD_REQ [31:29]: CMD_TARGET_IP_TYPE CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID CMD_REQ [23:16]: CMD_TYPE CMD_REQ [15:0]: CMD_OPCODE CMD_REQ [31:0]:
CH0 0x1 0x0 0x05 0xa 0x2005_000a
CH1 0x2 0x0 0x05 0xa 0x4005_000a

Recalibrate CH0 using the JAMB/AXI-Lite interface for CH0

  1. It is not required to write to the CMD_PARAM_* register as this OPCODE does not require any cmd_param.
  2. Write to the CMD_REQ(address=0x500_043c) with write_data=0x2005_000a .
  3. Read from CMD_RESPONSE_STATUS(address=0x500_045c) until you get the STATUS_COMMAND_RESPONSE_READY (Bit 0 of CMD_RESPONSE_STATUS register) equals 1.
  4. Clear the STATUS_COMMAND_RESPONSE_READY (Bit 0 of CMD_RESPONSE_STATUS register) Perform a Read-Modify-Write operation:
    1. Read from CMD_RESPONSE_STATUS register.
    2. Write_Data = Data in (a) & 0xffff_fffe (Change only bit 0).
    3. Write to address = 0x500_045c data= write_data from (b).

Recalibrate CH1 using the JAMB/AXI-Lite interface for CH1

Repeat the same steps as listed above. For Step 2, the write_data=0x4005_000a, because the CMD_TARGET_IP_TYPE for CH1 is 0x1 in this design.

Read the CH0 Calibration Status using the JAMB/AXI-Lite interface for CH0

  1. Read from read-only register STATUS(address=0x500_0400) till you get either bit_1/bit_0 is asserted.

    bit_0 = 1 means one or more EMIF instances have calibrated successfully.

    bit_1 = 1 means one or more EMIF instances have failed to calibrate successfully.

    bit_2 = 1 means one or more EMIF instances calibration still ongoing.

    bit_1 and bit_2 and bit_3 = 0 means no EMIF interface used in the design.

Read the CH1 Calibration Status using the JAMB/AXI-Lite interface for CH1

Repeat the same steps as for CH0, above.