Nios® V Processor: Lockstep Implementation

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ID 833274
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Nios® V Processor Lockstep 2. Overview 3. Controlling the Nios® V Processor Lockstep 4. Programming Model 5. Signals, Interfaces, and Build Parameters 6. Using Nios® V Processor Lock Step A. Document Revision History for the Nios® V Processor: Lockstep Implementation B. Appendix
1. About the Nios® V Processor Lockstep x
1.1. Nios® V Processor Lockstep Features
2. Overview x
2.1. Introduction 2.2. Main Principles 2.3. Operating Modes 2.4. Resets 2.5. LOGS Information
2.2. Main Principles x
2.2.1. System Phases 2.2.2. System States 2.2.3. Safety Mechanisms
2.2.2. System States x
2.2.2.1. Transitioning between System States
2.2.3. Safety Mechanisms x
2.2.3.1. Self-Checking Comparator 2.2.3.2. Timeout Timer 2.2.3.3. Enable Counters 2.2.3.4. Specialized Safety Mechanism
2.3. Operating Modes x
2.3.1. NORMAL and SILENT Modes
2.4. Resets x
2.4.1. Resetting CORE 2.4.2. Resetting OPTIONS 2.4.3. Resetting LOGS 2.4.4. Resetting Time Diversity Register
2.5. LOGS Information x
2.5.1. ALARMS 2.5.2. CONTEXT Determine the comparator mismatch location 2.5.3. STATISTICS 2.5.4. Reset LOGS
2.5.1. ALARMS x
2.5.1.1. Configuring Alarm Severity
3. Controlling the Nios® V Processor Lockstep x
3.1. Configuration Interface 3.2. fRNET Interface 3.3. Controlling the Elective Features
3.3. Controlling the Elective Features x
3.3.1. Applying Timeout and Comparator Blind Window 3.3.2. Injecting Fault 3.3.3. Downloading the CPU Software 3.3.4. Debugging the CPU Software using SILENT Mode 3.3.5. Resetting the CPU upon Fault Detection
3.3.1. Applying Timeout and Comparator Blind Window x
3.3.1.1. Timeout 3.3.1.2. Comparator Blind Window 3.3.1.3. Calculating the Blind Window and Timeout Period
3.3.2. Injecting Fault x
3.3.2.1. Root Fault Injection 3.3.2.2. Alarm Fault Injection
3.3.4. Debugging the CPU Software using SILENT Mode x
3.3.4.1. Entering SILENT Mode 3.3.4.2. SILENT Mode Limitation 3.3.4.3. Exiting SILENT Mode
3.3.5. Resetting the CPU upon Fault Detection x
3.3.5.1. Basic Reset Control
4. Programming Model x
4.1. Memory Map 4.2. Configuring fRSmartComp during Run-time 4.3. Unlocking and Locking Registers 4.4. Detailed Register Description
4.1. Memory Map x
4.1.1. Memory Map—Part 1 4.1.2. Memory Map—Part 2 4.1.3. Memory Map—Part 3
4.4. Detailed Register Description x
4.4.1. DCLSM Blind Window Control Register - DCLSM_BWCR 4.4.2. All Alarms’ Prior Alarms’ Fault Injection Register - ERRCTRL_ALL_ALARMS_PRIOR_AFI 4.4.3. INTREQ Configuration Register - ERRCTRL_INTREQ_CONF 4.4.4. Timeout Deadline and Status Register - ERRCTRL_TIMEOUT 4.4.5. Timeout Acknowledgment Register - ERRCTRL_TIMEOUT_ACK 4.4.6. Enable Key fRSmartComp Control Register - ERRCTRL_ENABLE_KEY 4.4.7. Root Fault Injection Control register - ERRCTRL_ROOT_INJ 4.4.8. Alarm Fault Injection Control register - ERRCTRL_ALARM_INJ 4.4.9. Event Mask Configuration register - ERRCTRL_MASKA and ERRCTRL_MASKB 4.4.10. Alarm Routing Configuration register - ERRCTRL_ROUTA and ERRCTRL_ROUTB 4.4.11. Error Controller PGO LOG Reset Control register - ERRCTRL_PGOLOGRST 4.4.12. PGO0 and PGO4 Configuration registers - ERRCTRL_PGO0 and ERRCTRL_PGO4 4.4.13. FN_MODEIN Control Register - ERRCTRL_FNMODEIN 4.4.14. FN_MODEOUT register - ERRCTRL_FNMODEOUT 4.4.15. All Alarms After Fault Injection - ERRCTRL_FNGIALARMS 4.4.16. Error Controller Context Register - ERRCTRL_FNGICTXT4 4.4.17. CMP Mismatch CONTEXT Registers - ERRCTRL_FNGICMPCTXT0 … ERRCTRL_FNGICMPCTXT3 4.4.18. STATISTICS registers: ERRCTRL_FNGISTAT0 and ERRCTRL_FNGISTAT4 4.4.19. State register - ERRCTRL_FNPERIPHGI4
5. Signals, Interfaces, and Build Parameters x
5.1. Configuration Interface 5.2. System Interface 5.3. fRNET Interface 5.4. IP Parameters
5.3. fRNET Interface x
5.3.1. CONFIG 5.3.2. INFO
6. Using Nios® V Processor Lock Step x
6.1. Instantiating Lockstep-Enabled Processor 6.2. Connecting Signals and Interfaces 6.3. Compiling Design 6.4. Implementing Startup Procedure 6.5. Applying Optional Injection for Validation 6.6. Detecting Faults 6.7. Handling Faults (Safety Use Case)
6.2. Connecting Signals and Interfaces x
6.2.1. Connecting Clock and Reset 6.2.2. Connecting Configuration Interface 6.2.3. Connecting System Interface
6.2.1. Connecting Clock and Reset x
6.2.1.1. Clock 6.2.1.2. Reset
6.2.3. Connecting System Interface x
6.2.3.1. Asynchronous Reset Interface 6.2.3.2. CPU Halt and Restart Acknowledgment Interface 6.2.3.3. Silent Mode Interface 6.2.3.4. Output Qualification (TERMS_LEFT and TERMS_RIGHT) 6.2.3.5. Interrupt Request (INTREQ) 6.2.3.6. ALARMS Interfaces 6.2.3.7. Connecting fRNET Interface
6.7. Handling Faults (Safety Use Case) x
6.7.1. UC_01: Standard Fail Safe or No Availability 6.7.2. UC_02: False Positive Avoidance 6.7.3. UC_03: Timeout on System Reset or After Fault Detection
1. About the Nios® V Processor Lockstep
2. Overview
3. Controlling the Nios® V Processor Lockstep
4. Programming Model
5. Signals, Interfaces, and Build Parameters
6. Using Nios® V Processor Lock Step
A. Document Revision History for the Nios® V Processor: Lockstep Implementation
B. Appendix

2.5.2. CONTEXT

The CONTEXT information provides additional information on top of the related alarm. It records context information only for the first occurrence of the related alarm. As such, the information is maintained (not refreshed) until the alarm itself is reset.
Table 15.  CONTEXT-related Registers
Configuration Interface fRNET Interface Description
ERRCTRL_FNGICTXT4 FRNET_GI_CTXT_4 Error Controller Context register
ERRCTRL_FNGICMPCTXT0 FRNET_GI_CMP_CTXT_0

Comparator context information of comparator slices 0 to 22.

Each bit is set to 1’b1 if the related comparator slice had a mismatch when the comparator mismatch was detected.

ERRCTRL_FNGICMPCTXT1 FRNET_GI_CMP_CTXT_1 Reserved
ERRCTRL_FNGICMPCTXT2 FRNET_GI_CMP_CTXT_2 Reserved
ERRCTRL_FNGICMPCTXT3 FRNET_GI_CMP_CTXT_3 Reserved

The following table maps each of the Nios® V CPU outputs into the fRSmartComp comparator slices during a mismatch event. Some slices may not be active, depending on the CPU and fRSmartComp configuration.

Table 16.   Nios® V CPU Outputs to Comparator Slices
Slices Number Slice ID Nios® V CPU Output
CPU Reset Acknowledge
0 RESETACK reset_req_ack
CPU Data Bus
1 BUS_D_AWADDR data_awaddr[31:0]
2 BUS_D_AWSIZE data_awsize[2:0]
3 BUS_D_AWLEN data_awlen[7:0]
4 BUS_D_CNTRL
  • data_awprot[2:0]
  • data_awvalid
  • data_wstrb[3:0]
  • data_wlast
  • data_wvalid
  • data_bready
  • data_arprot[2:0]
  • data_arvalid
  • data_rready
5 BUS_D_WDATA data_wdata[31:0]
6 BUS_D_ARADDR data_araddr[31:0]
7 BUS_D_ARSIZE data_arsize[2:0]
8 BUS_D_ARLEN data_arlen[7:0]
CPU Instruction Bus
9 BUS_I_AWADDR instr_awaddr[31:0]
10 BUS_I_AWSIZE instr_awsize[2:0]
11 BUS_I_AWLEN instr_awlen[7:0]
12 BUS_I_CNTRL
  • instr_awprot[2:0]
  • instr_awvalid
  • instr_awburst[1:0]
  • instr_bready
  • instr_arprot[2:0]
  • instr_arvalid
  • instr_arburst[1:0]
  • instr_rready
  • instr_wlast
  • instr_wvalid
  • instr_wlast
  • instr_wstrb[3:0]
13 BUS_I_WDATA instr_wdata[31:0]
14 BUS_I_ARADDR instr_araddr[31:0]
15 BUS_I_ARSIZE instr_arsize[2:0]
16 BUS_I_ARLEN instr_arlen[7:0]
Instruction TCM1 AXI4-Lite Bus
17 TCM1_I_BUS
  • itcs1_awready
  • itcs1_wready
  • itcs1_bvalid
  • itcs1_bresp[1:0]
  • itcs1_arready
  • itcs1_rdata[31:0]
  • itcs1_rvalid
  • itcs1_rresp[1:0]
Data TCM1 AXI4-Lite Bus
18 TCM1_D_BUS
  • dtcs1_awready
  • dtcs1_wready
  • dtcs1_bvalid
  • dtcs1_bresp[1:0]
  • dtcs1_arready
  • dtcs1_rdata[31:0]
  • dtcs1_rvalid
  • dtcs1_rresp[1:0]
Instruction TCM2 AXI4-Lite Bus
19 TCM2_I_BUS
  • itcs2_awready
  • itcs2_wready
  • itcs2_bvalid
  • itcs2_bresp[1:0]
  • itcs2_arready
  • itcs2_rdata[31:0]
  • itcs2_rvalid
  • itcs2_rresp[1:0]
Data TCM2 AXI4-Lite Bus
20 TCM2_D_BUS
  • dtcs2_awready
  • dtcs2_wready
  • dtcs2_bvalid
  • dtcs2_bresp[1:0]
  • dtcs2_arready
  • dtcs2_rdata[31:0]
  • dtcs2_rvalid
  • dtcs2_rresp[1:0]
CPU Custom Instruction Interface
21 CI_BUS
  • core_ci_data0[31:0]
  • core_ci_data1[31:0]
  • core_ci_alu_result[31:0]
  • core_ci_ctrl[31:0]
  • core_ci_enable
  • core_ci_op[3:0]
CPU ECC Interface
22 ECC_EVENT
  • cpu_ecc_status_ecc_source[3:0]
  • cpu_ecc_status_ecc_status[1:0]

Determine the comparator mismatch location

During a comparator mismatch (ALARM0 or ALARM1), the read value of FN_GI_CMP_CTXT_0 is 24’h000002, which equates to bit 1 is set. Thus, Slice 1 - BUS_D_AWADDR (data_ awaddr[31:0]) is the mismatch source.

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