GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

7.1. Transmitter Signals

Table 19.  Top-level Transmitter IP Core Signals
Signal Width Direction Description
JESD204C TX MAC Clocks and Resets
j204c_pll_refclk 1 Input TX PLL reference clock for the transceiver.
j204c_txlink_clk

1

Input

This clock is equal to the TX data rate divided by 66. Generated from the same PLL as txframe_clk.
j204c_txlclk_ctrl

1

Input

Generated from the same PLL as txlink_clk and txframe_clk. This clock control acts as a phase information for j204c_txlink_clk to handle CDC between j204c_txlink_clk and j204c_txframe_clk. This clock control is tied to 1 because j204c_txlink_clk is always the same or 2 times slower than j204c_txframe_clk. Every j204c_txlink_clk positive clock edge is aligned to j204c_txframe_clk positive clock edge.
j204c_txframe_clk

1

Input

This signal is synchronous with txlink_clk. Frequency is equal or 2x txlink_clk, based on the selected option for the frame clock frequency multiplier parameter. Generated from the same PLL as txlink_clk.

j204c_txfclk_ctrl

1

Input

Generated from the same PLL as j204c_txlink_clk and j204c_txframe_clk. This clock acts as a phase information of j204c_txframe_clk to handle CDC crossing from j204c_txframe_clk to j204c_txlink_clk. If FCLK_MULP = 1, this clock is tied to 1 because every j204c_txframe_clk positive clock edge is aligned to the j204c_txlink_clk positive clock edge. However, if FCLK_MULP=2, this signal pulses high for every j204c_txframe_clk period which has the positive clock edge aligned to the j204c_txlink_clk positive clock edge.
j204c_tx_avs_clk

1

Input

Avalon® memory-mapped interface clock.
reconfig_xcvr_clk 1

Input

PMA Avalon® memory-mapped interface clock. In duplex mode, both TX and RX share the same reconfiguration pins.
j204c_tx_rst_n

1

Input

Active-low asynchronous reset signal for MAC LL and TL.

Assertion triggers reset sequence to MAC and PHY. Reset sequence completion indicated by assertion tx_rst_ack_n.

Deassertion triggers out-of-reset sequence. Out of reset completion indicates by the deassertion of tx_rst_ack_n.

You must assert this reset signal if tx_avs_rst_n is asserted.

j204c_tx_avs_rst_n 1

Input

Active-low asynchronous reset signal for TX Avalon® memory-mapped interface.

This signal deasserts synchronous to tx_avs_clk.

j204c_tx_rst_ack_n 1 Output Asynchronous signal.

Acknowledgment indicator of the state of j204c_tx_rst_n.

reconfig_xcvr_reset 1 Input PMA Avalon® memory-mapped interface reset.

Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins.

Intel recommends that you tie this signal to tx_avs_rst_n.

pma_cu_clk 1

Input

The internal clock from the GTS Reset Sequencer Intel® FPGA IP to the transceiver logic.

Signal

Width

Direction

Description

Transceiver Interface
tx_serial_data

L

Output

Differential high speed serial output data. The clock is embedded in the serial data stream.
tx_serial_data_n

L

Output

Differential high speed serial output data. The clock is embedded in the serial data stream.
reconfig_xcvr_read

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_write

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_address

log2(L) +18

Input

Each transceiver lanes address is 18 bits wide. The upper bits are lane select.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_readdata

32

Output

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_writedata

32

Output

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_waitrequest

1

Output

Wait request signal.

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.
reconfig_xcvr_byteenable 4 Input

Byte enable signal. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access.

This signal is synchronous with reconfig_xcvr_clk.

Signal

Width

Direction

Description

JESD204C TX MAC Avalon® Memory-Mapped Interface
j204c_tx_avs_chipselect

1

Input

This signal is synchronous to tx_avs_clk.

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, Intel recommends that you tie this port to 1.

j204c_tx_avs_address

10

Input

This signal is synchronous to tx_avs_clk.

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

j204c_tx_avs_writedata

32

Input

This signal is synchronous to tx_avs_clk.

32-bit data for write transfers. The width of this signal and the j204c_tx_avs_readdata[31:0] signal must be the same if both signals are present.

j204c_tx_avs_read

1

Input

This signal is synchronous to tx_avs_clk.

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_tx_avs_readdata[31:0] signal to be in use.

j204c_tx_avs_write

1

Input

This signal is synchronous to tx_avs_clk.

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_tx_avs_writedata[31:0] signal to be in use.

j204c_tx_avs_readdata

32

Output

This signal is synchronous to tx_avs_clk.

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

j204c_tx_avs_waitrequest

1

Output

This signal is synchronous to tx_avs_clk.

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The GTS JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

Signal

Width

Direction

Description

JESD204C TX MAC Avalon® Streaming Interface (Data Channel)
j204c_tx_avst_data

M*S*N*WIDTH_MULP

Input

The minimum data width = M*S*N. This signal is synchronous to txframe_clk. Indicates the converter samples that is processed by TL.

This signal indicates a 64-bit user data (per lane) at txlink_clk clock rate, where 8 octets are packed into a 64-bit data width per lane. The data format is big endian.

If L=1 and M*S*N*WIDTH_MULP=64, the first octet is located at bit[63:56], followed by bit[55:48], and the last octet is bit[7:0]. If more than one lane is instantiated, Lane 0 data is always located in the upper 64-bit. Data lane L’s data is located at bit[63:0], with the first octet position for lane L is at bit[63:56].

j204c_tx_avst_control M*S*WIDTH_MULP*CS

Input

Control bits to be inserted as part of CS parameter.

This signal is synchronous to txframe_clk.

j204c_tx_avst_valid

1

Input

Indicates whether the data from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_tx_avst_ready signal is asserted.

  • 0—data is invalid
  • 1—data is valid

This signal is synchronous to txframe_clk.

j204c_tx_avst_ready

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

This signal is synchronous to txframe_clk.

Signal

Width

Direction

Description

JESD204C TX MAC Command (Command Channel)
j204c_tx_cmd_data

L*6

L*18

Input

Indicates a 6/18-bit user command (per lane) at txlink_clk clock rate. The data format is big endian. If more than one lane is instantiated, Lane 0 data is always located at the upper 18-bit or 6 bits of data, Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for Lane L at bit[17] or bit[5].

This signal is synchronous to txlink_clk.

If CRC-12 is enabled, width is L*6. If standalone command channel, width is L*18.

j204c_tx_cmd_valid

1

Input

Indicates whether the command from the application layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that data is always valid on every cycle when the j204c_tx_cmd_ready signal is asserted.

  • 0—data is invalid
  • 1—data is valid

This signal is synchronous to txlink_clk.

j204c_tx_cmd_ready

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept command. The Avalon® streaming sink interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

This signal is synchronous to txlink_clk.

Signal

Width

Direction

Description

JESD204C Interface
j204c_tx_sysref

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

Signal

Width

Direction

Description

JESD204C TX MAC CSR
j204c_tx_csr_l

4

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_f

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_m

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_cs

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_n

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_np

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_s

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_hd

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_cf

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to tx_avs_clk.

j204c_tx_csr_e 8

Output

LEMC period.

This signal is synchronous to tx_avs_clk.

Signal

Width

Direction

Description

JESD204C TX MAC Out-of-band (OOB)
j204c_tx_int

1

Output

Asynchronous signal.

Interrupt pin for the GTS JESD204C Intel® FPGA IP.

Interrupt is asserted when any error or synchronization request is detected. Configure the tx_err_enable register to set the type of error that can trigger an interrupt.

j204c_tx2rx_lbdata L*64 Output

This output is valid when the 66/64 Gearbox is available.

This signal is synchronous to txphy_clk.

Output as 64 bit width data after TX Gearbox. This signal is connected to RX IP (same signal name) for the Tx2Rx loopback function.

If L > 0, MSB of this bus is mapped to Lane 0. LSB is mapped to Lane L-1.

Note: For information about the transceiver PHY signals, refer to the Signal and Port Reference section in the GTS Transceiver PHY User Guide.
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