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1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Intel® FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. GTS JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the GTS JESD204C IP Design
4.8. Programming an FPGA Device
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7. Interface Signals
The GTS JESD204C Intel® FPGA IP uses the signals from the following interfaces.
Interface | Description |
---|---|
GTS JESD204C MAC to and from the PHY interface |
|
Avalon® memory-mapped interface |
|
Avalon® streaming interface |
|
Note: You should terminate any unused signals.