GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

3.1. Clocks

The GTS JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.

Table 10.   GTS JESD204C IP Clocks
Clock Signal Formula Description

TX/RX device clock

j204c_pll_refclk

PLL selection The PLL reference clock used by the TX Transceiver PLL or RX CDR. This is also the recommended reference clock to the Core PLL.

TX/RX link clock

j204c_txlink_clk

j204c_rxlink_clk

Line rate/66 The timing reference for the GTS JESD204C IP. The link clock is line rate divided by 66 because the link clock operates in a 66-bit data bus domain architecture after 64B/66B encoding.

TX/RX link clock control

j204c_txlclk_ctrl

j204c_rxlclk_ctrl

— This clock control acts as phase information for txlink_clk to handle CDC between txlink_clk and txframe_clk. This is tied to 1 because txlink_clk is always the same or 2 times slower than txframe_clk. Every txlink_clk edge is aligned to txfram_clk edge.

TX/RX frame clock

j204c_txframe_clk

j204c_rxframe_clk

(Link clock frequency*FCLK_MULP) MHz The frame clock as per the JESD204C specification. The frame clock is always 1x or 2x of the link clock.

TX/RX frame clock control

j204c_txfclk_ctrl

j204c_rxfclk_ctrl

— Generated from the same PLL as txlink_clk and txframe_clk, this clock control acts as phase information for txframe_clk to handle CDC between txlink_clk and txframe_clk. If FCLK_MULP=1, this can be tied to 1 because every txframe_clk edge is aligned to txlink_clk edge.

TX/RX Avalon® memory-mapped clock

j204c_tx_avs_clk

j204c_rx_avs_clk

— The configuration clock for the GTS JESD204C IP control and status registers through the Avalon® memory-mapped interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75 to 125 MHz.

TX PHY clock

j204c_phy_clk

Line rate/64

The PHY clock internally generated from the transceiver parallel clock for the TX path.
Transceiver reconfiguration clock

j204c_reconfig_clk

— The transceiver reconfiguration clock. During duplex mode, both TX and RX share the same reconfiguration pins.
GTS Reset Sequencer Intel® FPGA IP clock

pma_cu_clk

— The internal clock from the GTS Reset Sequencer Intel® FPGA IP to the transceiver logic.

Section Content
Device Clock
Frame Clock and Link Clock
GTS Reset Sequencer Intel FPGA IP Clock

Level Two Title