GTS JESD204C Intel® FPGA IP User Guide

ID 813959
Date 4/01/2024
Public
Document Table of Contents

3.4. Scrambler/Descrambler

Both the scrambler and descrambler are designed in a 64-bit parallel implementation and the scrambling/descrambling order starts from the first octet with MSB first.
Figure 6. Scrambling/Descrambling Order

The GTS JESD204C TX and RX IP core support scrambling/descrambling of converter data by implementing a 64-bit parallel scrambler per TX lane and a 64-bit parallel descrambler per RX lane. The scrambler and descrambler are located in the GTS JESD204C IP MAC interfacing to the Avalon® streaming interface. During operation, the scrambler and descrambler must be enabled. Unlike the previous generation's design, disabling of scrambler and descrambler is not allowed.

The scrambling polynomial is:

x58 + x39 + 1

The descrambler is able to self-synchronize in 58 bits. During typical application where the reset value of the scrambler seed is different from the converter device to the FPGA logic device, the correct user data is recovered in the receiver in one link clock cycle as the link data width is 64 bits.