Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

1.1. Agilex™ 5 Embedded Memory Features

The Agilex™ 5 FPGAs offer two main types of embedded memory blocks for designers to create custom memory solutions:
  • M20K Blocks:
    • Capacity: 20-kilobit (Kb)
    • Description: Dedicated memory resources providing a large number of independent ports (up to 4 independent ports). Ideal for larger memory arrays with high performance requirements.
    • Benefits:
      • High performance for data access.
      • Suitable for large memory designs.
      • Multiple independent ports for parallel access.
  • Memory Logic Array Blocks (MLABs)
    • Capacity: 640-bit
    • Description: Memory blocks configured from dual-purpose Logic Array Blocks (LABs). Offers flexibility for various memory designs, especially wide and shallow arrays. Well-suited for implementing functionalities such as:
      • Shift registers (commonly used in Digital Signal Processing)
      • Wide and shallow FIFO buffers (First-In-First-Out)
      • Filter delay lines
    • Benefits:
      • Flexibility for customized memory design.
      • Efficient for wide, shallow memory structures.
      • Can be configured as shift registers, FIFOs, or delay lines.
    • In Agilex™ 5 devices, you can configure each ALM in the MLAB as ten (32×2 bits) blocks. The Agilex™ 5 devices provide one 32×20 bits simple dual-port SRAM block per MLAB.
The Agilex™ 5 FPGAs offers a diverse range of memory access options with their embedded memory blocks:
  • Single-port: This mode provides a single access point for both reading and writing data. Only one operation (read or write) can occur at a time.
  • Simple dual-port: This mode provides simultaneous read and write access. It offers two independent ports but with a limitation: reading and writing to the same location at the same time is restricted.
  • Emulated true dual-port: This mode provides two independent ports that can perform simultaneous read and write operations on separate memory locations. It leverages FPGA fabric resources to emulate true dual-port behavior, potentially with slight performance or resource usage trade-offs compared to dedicated hardware true dual-port.
  • Simple quad-port: This mode provides four access points for enhanced data throughput. Similar to simple dual-port, simultaneous access to the same location for reading and writing can lead to data corruption.
  • ROM (Read-only memory): This mode provides read operations from the memory block only. Agilex™ 5 provides two options:
    • Single-port: Offers a single access point for reading data.
    • Dual-port: Offers simultaneous read operations from two independent ports.
Table 1.   Agilex™ 5 Embedded Memory FeaturesThis table summarizes the features supported by the Agilex™ 5 embedded memory blocks.
Features M20K MLAB
Maximum operating frequency
  • 1 GHz (simple dual-port RAM mode)
  • 600 MHz (true dual-port and simple quad-port RAM mode)

850 MHz

Total RAM bits (including parity bits) 20,480 bits 640 bits
Byte enable Supported Supported
Address Hold Supported (only in simple dual-port RAM mode) Supported for read address only.
Memory Initialization File (.mif) Supported Supported
Power-up state Output ports are cleared
  • Registered output ports: Cleared
  • Unregistered output ports: Refer to .mif for the memory contents.
Asynchronous/Synchronous Clears
  • Supports asynchronous clear on read address registers (only in simple dual-port and simple quad-port modes)
    Note: The actual data stored in the memory remains unchanged.
Output registers only.
Note: The actual data stored in the memory remains unchanged.
Same-port read-during-write
  • Single Port RAM: Output ports set to Old Data or Don't Care
  • Emulated True Dual Port RAM: Output ports set to New Data
  • Simple Quad Port: Output ports set to Don't Care
Output ports set to Don't Care
Note: When designing with Agilex™ 5, you can treat the unused ports as Don't Care during simulation. However, these ports have definite values in real hardware.
Mixed-port read-during-write
  • Simple Dual Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to Don't Care or New Data
  • Simple Quad Port: Output ports set to new_a_old_b
Output ports set to New Data, Old Data, or Don't Care
Note: When designing with Agilex™ 5, you can treat the unused ports as Don't Care during simulation. However, these ports have definite values in real hardware.
Error Correction Code (ECC) support
  • Built-in support ×32-wide simple dual-port mode
  • Parity bits
N/A
Force-to-Zero Supported N/A
Coherent read memory Supported N/A
Freeze logic Supported N/A
True dual port (TDP) dual clock emulator Supported N/A
Simple dual-port mixed width Supported N/A
FIFO buffer mixed width Supported N/A
Dual-clock mode Supported (only in simple dual-port RAM mode) Supported
Full synchronous memory Supported Supported
Asynchronous memory N/A Only for flow-through read memory operations
Write/read operation triggering Rising clock edges Rising clock edges