Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/15/2025
Public
Document Table of Contents

4.2.3.2.4. HDL Code from Parameterizable Macros Template

Alternatively, you can utilize the Verilog HDL or VHDL code from the Parameterizable Macros template.
  1. Right-click the HDL file and select Insert Template.
  2. In the Insert Template window, navigate to Verilog HDL or VHDL, and expand Intel Parameterizable Macros.
  3. Select from the available templates and click Insert.
    • sync_fifo—for SCFIFO
    • async_fifo—for DCFIFO or DCFIFO_MIXED_WIDTHS
    Figure 32. Inserting a Parameterizable Macro Template