Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813654
Date 8/16/2024
Public

2.3. Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
Figure 7.  Low Latency 40G Ethernet Intel® FPGA IP Design Example Block Diagram