Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.08.16 24.2 3.0.0
  • Updated the instructions in Compiling and Configuring the Design Example in Hardware section.
  • Updated the instructions in Testing the Design Example in Hardware section.
  • Added information about development kit in Hardware and Software Requirements section.
  • Updated Figure: Example Design Tab in the Low Latency 40G Ethernet Intel® FPGA IP Parameter Editor.
2024.04.01 24.1 2.1.0 Initial release.
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