1.2.1. Design Example Parameters

Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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Date 8/16/2024

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1.2.1. Design Example Parameters

Table 1. Parameters in the Example Design Tab
Parameter	Description
Select Design	Available example designs for the IP parameter settings. Single Instance of IP Core: Example designs instantiate a single instance of the IP.
Example Design Files	The files to generate for the different development phase. Simulation—generates the necessary files for simulating the example design. Synthesis—generates the synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format	The format of the RTL files for simulation—Verilog or VHDL.
Select Board	Provides supports for various development kits listed. The details of Intel FPGA development kits can be found on the Intel FPGA website. If this menu is greyed out, it is because no board is supported for the options selected such as synthesis checked off. If an Intel FPGA development board is selected, the `Target Device` used for generation will be the one that matches the device on the development kit. None: This option excludes the hardware aspects for the design example.