Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

2.3.1. Design Components

Table 4.  Design Components
Component Description
Low Latency 40G Ethernet Intel® FPGA IP

The Low Latency 40G Ethernet Intel® FPGA IP with the following configuration:

  • Device Family: Agilex 5
  • Protocol speed: 40GbE
  • Ready latency: 0
  • Enable SyncE: Disabled
  • PHY reference frequency: 156.25 MHz
  • Enable TX CRC insertion: Enabled
  • Enable link fault generation: Disabled
  • Enable preamble passthrough: Disabled
  • Enable MAC stats counters: Enabled
  • Enable Strict SFD check: Disabled
  • Enable MAC flow control: Disabled
  • Number of queues in priority flow control: 1
  • Enable JTAG to Avalon Master Bridge: Disabled
Reset Release Intel® FPGA IP The Reset Release Intel® FPGA IP outputs nINIT_DONE after finishing device initialization. User mode initialization can begin as soon as the nINIT_DONE signal asserts.
GTS Reset Sequencer Intel® FPGA IP Enable pma_cu_clk for the design.
GTS System PLL Clocks Intel® FPGA IP GTS System PLL Clocks Intel® FPGA IP that generates reference clock and system PLL clock.
IOPLL Intel® FPGA IP Intel FPGA Phase-Locked Loop (IOPLL Intel® FPGA IP) allows you to configure the settings of the I/O PLL.
In-System Sources & Probes Intel® FPGA IP In-system sources and probes debugging IP. The In-System Sources & Probes Intel® FPGA IP is available for all Intel device families supported by the Quartus® Prime software.
JTAG to Avalon® Master Bridge Intel® FPGA IP The JTAG to Avalon® Master Bridge Intel® FPGA IP is a collection of pre-wired components that provide an Avalon® Master using the new JTAG channel.
enable_cdr_clkout Disable
Level Two Title