Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.5. Compiling and Configuring the Design Example in Hardware

To compile hardware design example and configure it on your Agilex™ 5 device, follow these steps:

  1. Ensure that the hardware design example generation is complete.
  2. Launch the Quartus® Prime Pro Edition software and open the design example project file at <design_example_dir>/hardware_test_design/eth_ex_40g.qpf.
  3. Click Processing > Start Compilation.
  4. After a successful compilation, a .sof is available in <design_example_dir>/hardwarde_test_design.
  5. To program the hardware design example, launch the Clock Controller application and set the OUT0 frequency of Si5332-2 (U412) to 156.25 MHz.
    Figure 5. Clock Controller
  6. Click Tools > Programmer > Hardware Setup.
  7. Select a programming device,
  8. Select and add the Agilex™ 5FPGA E-Series 065B Premium Development Kit (ES1) to Quartus® Prime Pro Edition to which your session can connect.
  9. Ensure that Mode is set to JTAG.
  10. Click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
  11. In the row with your .sof, check the box for .sof.
  12. Select the check box in the Program/Configure column.
  13. Click Start.
    Power on reset is required after programming the Traffic test.
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