Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide

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ID 812857
Date 1/08/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Components 4. Document Revision History for Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide A. Additional Information
1. Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Clock Circuitry 3.5. Arduino Connectors 3.6. General User Input/Output 3.7. Power Supply
3.3. Configuration x
3.3.1. FPGA Programming over External Intel® FPGA Download Cable 3.3.2. Configuring the FPGA Using the Intel® Quartus® Prime Programmer 3.3.3. Selecting Internal Configuration Scheme 3.3.4. Generating a .pof File with ICB Settings 3.3.5. Programming Internal Flash Memory
3.4. Clock Circuitry x
3.4.1. General-Purpose Clock
3.6. General User Input/Output x
3.6.1. User-Defined DIP Switch 3.6.2. User-Defined LEDs
3.7. Power Supply x
3.7.1. Power Measurement 3.7.2. Power Distribution System 3.7.3. Temperature Sense
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Components
4. Document Revision History for Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide
A. Additional Information

2.4. Factory Default Switch and Jumper Settings

Figure 3. Switch Locations and Default Settings (Board Top)
Table 3.  Default SW3 DIP Switch Settings
Switch Function Default Position
1 User-defined On
2 User-defined On
3 User-defined On
4 User-defined On
5 User-defined On
6

BOOT_SEL: Use this switch to choose CFM0, CFM1, or CFM2 image as the first image in a dual-image configuration.

If BOOT_SEL is set to low, the first boot image is CFM0 image, If set to high, the first boot image is the CFM1 or CFM2 image. By default, the FPGA setting for this pin is tri-stated.

On
Table 4.  Default Jumper Settings
Jumper Function Setting
J6 Jumper for analog input channel #8. Default connection is to GND. Pins 2 and 3
J7 Jumper for analog input channel #7. Default connection is to potentiometer. Pins 2 and 3
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