Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide

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ID 812857
Date 1/08/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Components 4. Document Revision History for Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide A. Additional Information
1. Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Clock Circuitry 3.5. Arduino Connectors 3.6. General User Input/Output 3.7. Power Supply
3.3. Configuration x
3.3.1. FPGA Programming over External Intel® FPGA Download Cable 3.3.2. Configuring the FPGA Using the Intel® Quartus® Prime Programmer 3.3.3. Selecting Internal Configuration Scheme 3.3.4. Generating a .pof File with ICB Settings 3.3.5. Programming Internal Flash Memory
3.4. Clock Circuitry x
3.4.1. General-Purpose Clock
3.6. General User Input/Output x
3.6.1. User-Defined DIP Switch 3.6.2. User-Defined LEDs
3.7. Power Supply x
3.7.1. Power Measurement 3.7.2. Power Distribution System 3.7.3. Temperature Sense
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Components
4. Document Revision History for Intel® MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide
A. Additional Information

1.1. Board Component Blocks

This evaluation kit features the following major component blocks. For a detailed description of the board components, see Board Components.

  • Intel® MAX® 10 FPGA, 10M08SAE144C8G, (or ES variant)
    • 8,000 logic elements (LE)
    • 378 kilobits (Kb) M9K memory
    • 32–172 Kb user flash memory
    • One ADC, 1 million samples per second (MSPS), 12-bit
  • FPGA configuration circuitry
    • JTAG header for external Intel® FPGA Download Cable, Intel® FPGA Download Cable II, or Intel® FPGA Ethernet Cable
    • Flash storage for two configuration images (factory and user)
    • Dual-image self-configuration via Programmer Object File (.pof)
    • Temporary engineering debug of FPGA design via SRAM Object File (.sof)
  • On-Board clocking circuitry
    • 50 MHz oscillator connected to FPGA global clock input
  • General user I/O
    • 8 analog input I/O, 14 Arduino I/O, 40 general purpose I/O
    • 5 red user-defined LEDs
    • One green LED to show power from USB cable
  • Push button and DIP switches
    • One reconfiguration push button (SW2)
    • One device-wide reset of all registers, push button (SW1)
    • User DIP switch (SW3)
  • Power
    • The board is powered by USB cable (from PC or wall jack)
    • One green power-on LED (D6)
    • Probe points for manual, multi-meter measurement of current to calculate power consumption (TP2 - TP5) or to verify voltages on the selected internal nodes (TP1, TP6 - TP9)
Figure 1. Example Intel® MAX® 10 Evaluation Kit Block Diagram - Power Solution 2 (DK-DEV-10M08E144-B)
Figure 2. Example Intel® MAX® 10 Evaluation Kit Block Diagram - Power Solution 1 (EK-10M08E144)
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