Intel® Simics® Simulator for Intel® FPGAs: User Guide

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ID 784383
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

5.5.3. Events

Intel® Simics® simulator is an event-driven simulator. Depending on the type of event, the resolution of them is different. Events are handled by event queues. An event is scheduled to occur in the future by adding this into a queue. There are different type queues with a specific resolution to handle these events.

Event Queue Notes
Time(PS) Resolution of 1 ps. Used by providers such as clocks or processors.
Step Resolution of a CPU step. Events are programmed to occur triggered on a CPU step.
Cycle Resolution of a CPU cycle. Events are programmed to occur triggered on a CPU cycle. These are the most common events.

Based on the queue resolution, the Intel® Simics® simulator evaluates (every step, cycle, and ps) if an event is ready to be triggered. If this is the case, the event is processed, and it is removed from the queue or rescheduled in the queue depending on how the event was configured.

Events with step resolution are useful for debugging (execute 1 step at a time, stop after executing 3 steps, and so on). Events with time resolution are rather independent from the flow of execution (sector read operation on the hard disk finishes in 1 ms). 

# Intel Simics simulator CLI 

# Runing 5 steps using run command

simics> run 5 steps
Processor agilex.hps.core[0] is stalling - may take a long time to finish.
# Running 5 steps using stepi command

simics> stepi 5
[agilex.hps.core[0]] v:0xffff800008010a84 p:0x8000000002010a84  add sp, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a88 p:0x8000000002010a88  sub x0, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a8c p:0x8000000002010a8c  tbnz w0, #14, 0xffff800008010a9c
[agilex.hps.core[0]] v:0xffff800008010a90 p:0x8000000002010a90  sub x0, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a94 p:0x8000000002010a94  sub sp, sp, x0
# Run 5 cycles using step-cycle command

simics> step-cycle 3
[agilex.hps.core[0]] v:0xffff800008011334 p:0x8000000002011334  stp x28, x29, [sp, #224]
[agilex.hps.core[0]] v:0xffff800008011338 p:0x8000000002011338  add x21, sp, #0x150
[agilex.hps.core[0]] v:0xffff80000801133c p:0x800000000201133c  mrs x28, sp_el0

In the case of events cycle resolution, events are triggered in the following order:

  • All events posted for this specific cycle, except step execution.
  • For each step scheduled for execution on this cycle.
  • All events scheduled for that specific step.
  • A step execution.

Events belonging to the same category are executed in FIFO order: posted first is executed first.

The step and cycle events posted by the device models can be observed with the print-event-queue as shown in the following capture. Under these categories, you can find the interrupts and exceptions. 

# Intel Simics simulator CLI 

simics> print-event-queue
--------------------------------------------------
Cycle      Object             Description 
--------------------------------------------------
      46  agilex.hps.uart0    regs.xmit_proceed 
  915499  agilexhps.timer[0]  aarch64.cntp.timeout
39641472  agilex.phy0         tx_led.off 
39649472  agilex.phy0         rx_led.off
--------------------------------------------------

In the above capture, you can see that for each event in the list there is information about the number of cycles pending to trigger the event, the object that posted it and a brief description about it.

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