The SDM is a triple-redundancy processor that runs the firmware that manages configuration and other features such as security. This document focuses on how the SDM interacts with the QSPI flash devices via the QSPI controller that is part of the FPGA hardware inside the chip. The following figure illustrates the simple block diagram of the SDM, the QSPI controller, and the QSPI flash device.

Upon device power up, the SDM loads the bootrom code that was hardcoded during manufacturing. The bootrom identifies the bitstream source by sampling the Mode Select (MSEL) pins setting set by the customers. If bootrom identifies the QSPI as the bitstream source, the bootrom reads the SDM firmware from the QSPI by using simple read command with a clock at a reasonable speed, i.e. 25 MHz to make sure the SDM can load the firmware successfully.

Once the SDM loads firmware from the QSPI flash, the SDM firmware carries out a series of actions to optimize the performance to access the flash subsequently. The SDM firmware initially runs at slower clock (AS_CLK) speed, i.e. 12.5 MHz to read the Serial Flash Discoverable Parameters (SFDP) table from the flash device and determine the appropriate initialization and calibration based on the SFDP table. Once the SDM firmware gathers the necessary information, the SDM firmware then initializes both, the QSPI flash device and the QSPI controller registers, followed by the calibration to optimize the interaction between the QSPI controller and the flash device, so that the SDM firmware can access the flash at faster clock speed.

Knowing the above ASx4 configuration process, you can now identify a QSPI flash that meets the SFDP standard to fulfill the SDM firmware requirements. With the compatible QSPI flash device, it is ready for ASx4 configuration in SDM-based devices. You can generate and program the programming file to the QSPI flash device, using Quartus Programmer, Configuration Debugger Tool or third-party programmer.