Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 9/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

8.3.1. Steps to Simulate the Design Example

  1. Navigate to <Design Example Directory>/example_testbench/
  2. Type appropriate command for your simulator:
    Simulator Command
    VCS sh run_vcs.sh
    VCSMX sh run_vcsmx.sh
    Questasim -c -do run_vsim.tcl
    Xcelium sh run_xcelium.sh
  3. Observe simulation output. The successful simulation displays a Testbench Complete message.

The following sample output illustrates a successful simulation test run for the Ethernet Subsystem IP core design example testbench. 

TBINFO:  Ref clock is 156.25 MHz
TBINFO:        300335000000     Port 0 - Waiting for EHIP READY
TBINFO:        425955000000     Port 0 - EHIP READY is 1
TBINFO:        425955000000     Port 0 - Waiting for EHIP RX Block Lock
TBINFO:        438285000000     Port 0 - EHIP RX Block Lock  is high
TBINFO:        438285000000     Port 0 - Waiting for RX PCS Ready
TBINFO:        438300000000     Port 0 - RX deskew locked
TBINFO:        438300000000     Port 0 - RX lane aligmnent locked
TBINFO:        438300000000     Port 0 - Waiting for TX Lanes Stable
TBINFO:        438300000000     Port 0 - TX enabled
TBINFO:        438300000000     Port 0 - Checking EHIP Ready & Rx Block Status Register
TBINFO:        438310000000     Address offset = 00202114, WriteData = 00000003
TBINFO:        438330000000     Address offset = 00202514, WriteData = 00000003
TBINFO:        439210000000     Address offset = 00202114, WriteData = 00000000
TBINFO:        440100000000     Address offset = 00202514, WriteData = 00000000
TBINFO:        443250000000     Address offset = 002020d8, ReadData  = 00000000
TBINFO:        444660000000     Address offset = 002024d8, ReadData  = 00000000
TBINFO:        444667000000     Port 0 - Sending  Packet 1
TBINFO:        444694000000     Port 0 - Sending  Packet 2
TBINFO:        444722000000     Port 0 - Sending  Packet 3
TBINFO:        444749000000     Port 0 - Sending  Packet 4
TBINFO:        444776000000     Port 0 - Sending  Packet 5
TBINFO:        444804000000     Port 0 - Sending  Packet 6
TBINFO:        444831000000     Port 0 - Sending  Packet 7
TBINFO:        444858000000     Port 0 - Sending  Packet 8
TBINFO:        444885000000     Port 0 - Sending  Packet 9
TBINFO:        444913000000     Port 0 - Sending  Packet 10
TBINFO:        445347000000     Port 0 - Received Packet 1
TBINFO:        445379000000     Port 0 - Received Packet 2
TBINFO:        445412000000     Port 0 - Received Packet 3
TBINFO:        445442000000     Port 0 - Received Packet 4
TBINFO:        445471000000     Port 0 - Received Packet 5
TBINFO:        445506000000     Port 0 - Received Packet 6
TBINFO:        445533000000     Port 0 - Received Packet 7
TBINFO:        445563000000     Port 0 - Received Packet 8
TBINFO:        445590000000     Port 0 - Received Packet 9
TBINFO:        445620000000     Port 0 - Received Packet 10
TBINFO:        447080000000     Address offset = 002020d8, ReadData  = 0000000a
TBINFO:        448490000000     Address offset = 002024d8, ReadData  = 0000000a
TBINFO:        449900000000     Address offset = 00202010, ReadData  = 00000000
TBINFO:        451310000000     Address offset = 00202410, ReadData  = 00000000
**
** Testbench complete.
**
*****************************************
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