Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 9/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping 3.4. Analog Parameter Options
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Asynchronous Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

Document Version Quartus® Prime Version Changes
2024.09.16 24.2 Made the following Changes:
  • Corrected the Supported Features table in the Introduction section to reflect the correct ports support for E-Tile and F-Tile.
  • Corrected the bit values and updated the description for bits 5 and 6 in the HSSI Ethernet Port X Status section, as they are not applicable to E-Tile and F-Tile.
  • Updated the Steps to Generate the Example Design section to include the available Target Development Kits.
2024.07.08 24.2 Made the following changes:
  • Added the following parameters in Ethernet Subsystem IP Parameters: HSSI:
    • Enable Multi Tile
    • Tile Number
    • SYSPLL_RATE_GUI
    • SYSPLL_CUSTOM_GUI
    • Added the following ranges to the Port_PORT<n>_PROFILE:
      • 100GCAUI-4 (E-Tile and F-Tile)
      • 100GAUI-2 (E-Tile and F-Tile)
      • CPRI (E-Tile only)
    • Added a note to the Enable TX PTP Classifier parameter stating that this feature is not supported in F-Tile Dynamic Reconfiguration.
    • Added new topic: Analog Parameter Options.
  • Added steps for AN/LT Dynamic Reconfiguration in Auto-Negotiation and Link Training section.
  • Added i_clck_sys in Clocks under Interfaces and Signals topic.
  • Removed the following clock modes that do not support F-Tile from the o_p<n>_clk_pll signal in Clocks:

    • 402.83203125 MHz or higher for all Ethernet modes without FEC, with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91). The system PLL must be of 805.6640625 MHz frequency or higher.

    • 161.1328125 MHz or higher for 10GE without enabled PTP. The system PLL must be of 322.265625 MHz frequency or higher.

    • Custom system PLL frequency divided by 2, if custom system PLL frequency is used.
  • Added new bits in HSSI Ethernet Port X Status.
    • 29:29
    • 28:28
    • 27:27
2024.04.03 24.1 Made the following Changes:
  • Updated resource utilization numbers due to changes from Nios® II to Nios® V.
  • Added these devices in the supported features section.
    • 100Gbe GAUI-2 for E-Tile
    • 100Gbe GAUI-1 for E-Tile
    • 100GCAUI-4 and 100G AUI-4 for F-Tile
  • Updated Port_PORT<n>_PROFILE parameter GUI rate options in the Ethernet Subsystem Parameters.
  • Corrected the following path in Steps to generate Routing Delay for PTP Enabled Designs.
    • <design example>/ex_ss/hssi_ss_<version>/synth/hssi_ss_ptp_report_dl_path_delay.tcl
    • quartus_sta -t hssi_ss_ptp_report_dl_path_delay.tcl <project_name>
  • Corrected the following description for bit 5:0 in Interface Attribute Port X Parameters.
    • 6'b011011:100GCAUI-4/100GAUI-4
    • 6'b010111: 50GAUI-2/50GLAUI-2
2023.12.08 23.4 Made the following changes:
  • Updated disclaimer statement in Introduction.
  • Updated Resource Utilization table for E-Tile and F-Tile in Resource Utilization.
  • Added the new IP parameter: Enable SFE/PFC Queue Buffering in Ethernet Subsystem Intel FPGA IP Parameters.
  • Added new topic: Priority Flow Control.
  • Updated Flow Control Signals table in Flow Control.
  • Added QuestaSim* (VHDL/Verilog) (Excluding QuestaSim FPGA Edition) in Supported Simulators.
  • Corrected Enable ECC Protection description in Ethernet Subsystem Intel FPGA IP Parameters: HSSI.
  • Added new IP parameter: Enable System PLL for F-Tile in Ethernet Subsystem Intel FPGA IP Parameters: HSSI.
  • Added AXI configuration in Ethernet Subsystem - IP Configuration Tab.
  • Corrected the 40G/50G speed in AXI Stream Bridge table and added a note stating that the F-Tile system PLL IP is integrated when Enable System PLL for F-Tile parameter is turned ON.
  • Corrected the AN/LT section description in Auto-Negotiation and Link Training.
  • Added a new row p<n>_ss_app_st_rx_tuser_tlast_buf_pkt_truncation<segment number> to the AXI-ST RX Client Interface Signals table in AXI-ST Client Interface.
  • Updated Flow Control Signals section.
  • Added a new table Reset Signals-Block level in Resets.
  • Added the following new sections in Subsystem Registers of Register Description section.
    • Priority Flow Control TX Queue Statistics
    • Priority Flow Control RX Queue Statistics
    • Priority Flow Control TX Queue Threshold
    • Priority Flow Control RX Queue Threshold
    • F-Tile DR Controller Status
  • Updated table F-Tile Register Map for Port Enabled with Ethernet Protocol table in F-Tile Address Maps.
  • Removed F-Tile Register Map for per-channel Transceiver Reconfiguration Interface.
  • Added a new section F-Tile DR Controller Register Map.
2023.10.02 23.3 Made the following changes:
  • Updated register description table for bits[4:1] for E-Tile in Ncsi_get_link_status.
  • Updated Dynamic Reconfiguration Extension Subsystem section.
  • Updated resource utilization table for F-Tile in Resource Utilization.
2023.08.29 23.2
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
    • 200GbE GAUI-8 for F-Tile device.
  • Added Device Family Support section.
  • Updated Release Information section.
  • Added 200GbE GAUI-4/200GbE GAUI-8 port in Feature Description.
  • Updated Supported Ethernet Features table in Supported Features.
  • Added Enable ECC protection parameter in General Configuration tab.
  • Added the following parameters in Port_<port_number:1-16>Port_<n>_configuration of Ethernet Subsystem Intel FPGA IP Parameters: HSSI
    • Dynamic Reconfiguration
    • 100G Partial Reconfiguration
  • Added the following parameters to General Options in F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem –IP Configuration Tab table.

    • Enable debug endpoint for transceiver toolkit

    • Enable debug endpoint for Ethernet toolkit

    • Enable asynchronous adapter clocks
    • Enable dedicated CDR clock output
    • Include 40GE
    • Include 32bit sof CWBIN counters
  • Added AN channel location 0 under ANLT Options tab.
  • Added new chapter Subsystem IP Blocks.
    • Added new section AXI Stream Bridge.
    • Added IEEE 1588V2 PTP chapter.
  • Added Auto-Negotiation and Link Training chapter.
    • Added ANLT for E-Tile section.
    • Added ANLT for F-Tile section.
  • Added get_hssi_profile for E-Tile section.
  • Updated get_hssi_profile for F-Tile
  • Added set_hssi_profile for E-Tile section.
  • Updated set_hssi_profile for F-Tile.
  • Updated read_MAC_statistic table in Subsystem Abstraction Layer(SAL) Commands.
  • Updated get_mtu section.
  • Updated get_csr for E-Tile section.
  • Added Register Description for E-tile in Ncsi_get_link_status section.
  • Added a table signals mapping between 100G and 25G AXI-ST on the same interface in Dynamic Reconfiguration Extension Subsystem.
  • Updated F-Tile Address Maps section.
  • Updated E-Tile supported Example Design Variants table in Ethernet SS IP Design Example.
  • Added Steps to generate routing delay for F-Tile section in Running the Hardware Tests.
  • Added a new topic Clock Connections for SyncE Operation on F-Tile in Recommended Clock Connections.
  • Splitted F-Tile Register Map for Port Enabled with Ethernet Protocol into two tables in F-Tile Address Maps:
    • F-Tile Register Map for Port Enabled with Ethernet Protocol Port Enabled with Ethernet Protocol
    • F-Tile Register Map for per-channel Transceiver Reconfiguration Interface
  • Removed the DR support from the table F-Tile Support Example Design Variants in Ethernet SS IP Example Design.
2023.04.14 23.1
  • Updated instances of Transceiver Subsystem IP name to Ethernet Subsystem
  • Updated Introduction section with additional data rates and version.
  • Updated Ethernet Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 23.1 in Getting Started section.
  • Updated Feature Description section with additional ports details.
  • Updated Supported Features section with additional ports details.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Ethernet Subsystem Intel FPGA IP Parameters: HSSI table in Parameter Editor Parameters section.
  • Updated E-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated F-Tile Ethernet Subsystem Intel FPGA IP Parameters: Ethernet Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Added new section F-tile HSSI Port to PMA Channel Mapping.
  • Updated AXI-ST Tx Client Interface Signals and AXI-ST Rx Client Interface Signals tables in AXI-ST Client Interface.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clock Signals table in Clocks section.
  • Updated Alternate Clock Connections for MAC Async Client FIFO section.
  • Updated F-tile Supported Example Design Variants table in HSSI SS IP Example Design section.
  • Added new section Supported Simulators.
  • Updated Running the Simulation Tests section.
2023.01.13 22.4
  • Updated Introduction section with additional data rates.
  • Updated Transceiver Subsystem Intel FPGA IP Features table in Supported Features section.
  • Updated version to 22.4 in Getting Started section.
  • Updated Supported Ethernet Protocols table in Supported Features section.
  • Updated Transceiver Subsystem Intel FPGA IP Parameters: HSSI table and F-Tile Transceiver Subsystem Intel FPGA IP Parameters: HSSI Subsystem – IP Configuration Tab table in Parameter Editor Parameters section.
  • Updated AXI-ST Tx Client Interface Signals table and AXI-ST Rx Client Interface Signals table in AXI-ST Client Interface section.
  • Updated Flow Control Signals table in Flow Control section.
  • Updated Serial Interface Signals table in Serial Interface section.
  • Updated Clocks Signals table in Clocks section.
  • Updated Value After Reset in Device Feature Header Hi section.
  • Updated Byte Offset information in the following sections:
    • Version
    • Feature List
    • Interface Attribute Port X Parameters
    • HSSI Command/Status
    • HSSI Read Data
    • HSSI Write Data
    • HSSI Ethernet Port X Status
  • Added F-tile ANLT Port Register Map and F-tile PTP Tile Adapter Register Map sections under Register Descriptions section.
2022.11.01 22.3 Initial release.
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