Ethernet Subsystem Intel® FPGA IP User Guide

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Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3. Subsystem Abstraction Layer (SAL)

The following figure illustrates the Subsystem Abstraction Layer (SAL).

The Subsystem Abstraction Layer (SAL) consists of a NIOS processor and an M20K memory which hosts the NIOS firmware. The main functionality of the SAL is to provide an abstraction layer for the external software to access the functionality of the Ethernet Subsystem via MMIO requests through the AXI-Lite interface.

Figure 4. Subsystem Abstraction Layer (SAL) Block Diagram

The software running on the host CPU communicates with the NIOS soft processor via four 32-bit Subsystem registers: HSSI Command/Status, HSSI Control/Address, HSSI Write Data and HSSI Read Data CSRs.

The external software can make simple “peek/poke” style transaction requests to the NIOS using a traditional asynchronous handshake procedure described below. Please take note that the NIOS processor is not optimized for speed. It is expected to take a few microseconds to complete and acknowledge most transactions.

Handshake procedure:

  • CPU fills control/address control register and commands to be executed.
  • CPU subsequently asserts write/read command bit in command/status control register.
  • NIOS observes and executes request.
  • NIOS asserts BUSY bit in HSSI Command/Status register.
  • NIOS asserts ACK_TRANS bit and clears the BUSY bit in the HSSI Command/Status register upon completion.
  • CPU observes ACK_TRANS and ERROR bit status and write 0 to clear Command/Status register

The Command/Status register is used to trigger application specific functions in the firmware (written in C code). The host would write the SAL command into Control/Address register as desired then write to Command/Status to start the function. An optional return value will appear in the Read Data register.

Table 14.  Subsystem Abstraction Layer Commands
HSSI Command/Status   HSSI Control/Address   HSSI Write Data HSSI Read Data
[6:5] - ROffset [4:4] - Error [3:3] - BUSY [2:2] - ACK_TRANS [1:1] - WRITE_CMD [0:0] - READ_CMD     [7:0] - SAL Command    
0 0 0 0 1 0 reserved[31:7] 0x0 - NOP    
0 0 0 0 0 1 reserved[31:16] 0 - 255- Port[15:8] 0x1 - get_hssi_profile   [19:0] - Current Profile
0 0 0 0 1 0 reserved[31:16] 0 - 255- Port[15:8] 0x2 - set_hssi_profile [19:0] - Next Profile  
0 0 0 0 0 1 LSB[31] reserved[30:21] 0-30 - Counters[20:16] 0 - 255- Port[15:8] 0x3 - read_MAC_statistic    
0 0 0 0 0 1 reserved[31:16] 0 - 255- Port[15:8] 0x4 - get_mtu    
Register Offset[1:0] 0 0 0 1 0 Address[25:2] 0x5 - set_csr [31:0] - Write CSR Data  
Register Offset[1:0] 0 0 0 0 1 Address[25:2] 0x6 - get_csr   [31:0] - Read CSR Data
0 0 0 0 1 0 reserved[31:16] 0 - 255- Port[15:8] 0x7 - enable_loopback    
0 0 0 0 1 0 reserved[31:16] 0 - 255- Port[15:8] 0x8 - disable_loopback    
0 0 0 0 1 0 reserved[30:18] 0 - 1 - RX[17] 0 - 1 - TX[16] 0 - 255- Port[15:8] 0x9 - reset MAC statistic    
0 0 0 0 1 0 reserved[31:16] 0 - 255- Port[15:8] 0xA - set_mtu    
0 0 0 0 0 1 reserved[31:16] 0 - 255- Port[15:8] 0xB - ncsi_get_link_status   [31:0] - Read CSR Data
0 0 0 0 0 0     0xC - 0xFE - reserved    
0 0 0 0 0 1 reserved[31:7] 0xFF - firmware_version   [31:0] Firmware Version

The following example demonstrates how the host software would execute the get_mtu and enable_internal_loopback SAL commands on port 0 channel 0.

Command:get_mtu

  • Write HSSI Control/Address Register: 0x4 to bit [7:0](SAL Command), 0x0 to bit[11:8](Port), 0x0 to bit[15:12](Channel).
  • Write HSSI Command/Status Register to configure READ_CMD = 1, WRITE_CMD = 0
  • Poll ACK_TRANS, BUSY and ERROR bits of HSSI Command/Status Register.
  • If ACK_TRANS = 1 and BUSY/ERROR = 0, read HSSI Read Data Register for MTU value.
  • Write 0x0 to clear HSSI Command/Status Register and HSSI Control/Address Register.

Command:enable_loopback

  • Write HSSI Control/Address Register: 0x7 to bit [7:0] (SAL Command), 0x0 to bit[11:8](Port), 0x0 to bit[15:12](Channel).
  • Write HSSI Command/Status Register to configure READ_CMD = 0, WRITE_CMD = 1, ACK_TRANS = 0
  • Poll ACK_TRANS, BUSY and ERROR bits of HSSI Command/Status Register.
  • If ACK_TRANS = 1 and BUSY/ERROR = 0, loopback is enabled successfully
  • Write 0x0 to clear HSSI Command/Status Register and HSSI Control/Address Register

SAL Hardware will continue polling HSSI Command/Status Register to determine any new request from software.

If the READ_CMD = 1, WRITE_CMD = 0 and ACK_TRANS = 0, it indicates software has issued a read command to SAL registers.

  • SAL Hardware reads the HSSI Control/Address register
  • SAL Hardware asserts BUSY at bit[3] and perform action based on SAL command.
  • Upon successful completion:
    • SAL Hardware asserts the ACK_TRANS at bit[2], de-asserts BUSY at bit[3], de-asserts ERROR at bit[4] of HSSI Command/Status register and writeback the read data in HSSI Read Data register.
  • If command does not complete within the Timeout threshold (10ms):
    • SAL Hardware exits from command execution
    • SAL Hardware de-asserts BUSY at bit[3] and asserts ERROR at bit[4] of HSSI Command/Status register

If the READ_CMD = 0, WRITE_CMD = 1 and ACK_TRANS = 0, it indicates software issued a write command to SAL registers.

  • SAL Hardware reads the HSSI Control/Address register and HSSI Write Data register
  • SAL Hardware asserts BUSY at bit[3] of HSSI Command/Status register.
  • Upon successful completion:
    • SAL Hardware asserts the ACK_TRANS at bit[2], de-asserts BUSY at bit[3], de-asserts ERROR at bit[4] of HSSI Command/Status register.
  • If command does not complete within Timeout threshold (10ms):
    • SAL Hardware exits from command execution
    • SAL Hardware de-asserts BUSY at bit[3] and asserts ERROR at bit[4] of HSSI Command/Status register.

SAL Command Requirements:

  • SAL Hardware is responsible for setting the ACK_TRANS bit, but software must clear this bit.
  • SAL Hardware will read the Command/Status register only when it is in idle state and not executing any command.
  • It is the responsibility of software to avoid writing commands when SAL hardware is executing a command. There will be no indication to show the hardware is idle, software must ensure the previous command is completed before writing another command.
  • ERROR bit of Command/Status register is valid only when ACK_TRANS bit is asserted.
  • BUSY bit of Command/Status register will be asserted when the SAL hardware is processing a command. The bit will be de-asserted upon successful command completion or forceful exit due to timeout.
  • For DR and enable/disable loopback SAL sequences, the whole operation might take more than 10ms and timeout does not apply for these sequences. Instead, a polling method is implemented where a counter is used to poll the DR status and it will exit with an error when the polling counter expires.

The following diagram illustrates the connectivity between NIOS and the SAL CSR. The SAL command you wrote is qualified with the Read/Write command from the HSSI Command/Status CSR. Each of the SAL commands can be translated into individual PIO input.

Figure 5. Connection Between NIOS and SAL CSR

NIOS will constantly sample the PIO input to determine what action is invoked by you. Upon completion of the SAL command, NIOS will return the status to HSSI Command/Status Register through PIO output.


Section Content
Subsystem Abstraction Layer (SAL) Commands

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