Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Public

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7.1.18. Priority Flow Control TX Queue Threshold

Description: PFC TX Queue high and low thresholds

Byte Offset: 0x4060 + 4 x (0 - 7

Addressing Mode: 32 bits

Bit Type Reset Description
31:5 RO 0 Reserved
15:0 RO 0b100

cfg_tx_th[Q]

TX threshold expressed as a percentage of TX Queue size
  • 0b000 - 0%
  • 0b001 - 12.5%
  • 0b010 - 25%
  • 0b011 - 37.5%
  • 0b100 - 50%
  • 0b101 - 62.5%
  • 0b110 - 75%
  • 0b111 - 87.5