Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 25.0.0
The Ethernet Subsystem Intel FPGA IP, F-Tile variant, is early access and provided for evaluation purposes. Features are subject to change. Please consult the release notes for production status.

The Ethernet Subsystem Intel FPGA IP is a subsystem IP that includes a configurable, Media Access Control (MAC) and Physical Coding Sublayer (PCS) presenting a consistent interface to user logic. It consists of 20 ports. Depending on the tile chosen, each port is implemented based on either the Agilex™ 7 E-Tile Hard IP for Ethernet Intel FPGA IP Core or the F-Tile Hard IP for Ethernet Intel FPGA IP core.

This IP provides a seamless and fast way to instantiate a multi-port design, given that it integrates the required discrete Hard IP and Soft IP ingredients. Furthermore, the Subsystem IP provides a user interface to facilitate enabling required features and parameters of operation.

For E-Tile, this subsystem IP provides Ethernet data rate profiles of 10Gbps, 25Gbps, and 100Gbps with optional RS-FEC and 1588 Precision Time Protocol (PTP). The subsystem also provides profiles for PCS, OTN, FlexE and CPRI.

For F-Tile, this subsystem IP provides Ethernet data rate profiles of 10Gbps, 25Gbps, 40Gbps, 50Gbps, 100Gbps, 200Gbps, and 400Gbps with optional RS-FEC and 1588 Precision Time Protocol (PTP). Quartus® Prime software version 23.2 supports only Media Access Control (MAC) and Physical Coding Sublayer (PCS) sub-profile.