Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Public

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1.4. Resource Utilization

The following tables present preliminary resource utilization of the Ethernet Subsystem IP across Ethernet rates, IP Core variations, and tiles.
Table 5.  Ethernet Subsystem Intel FPGA IP Resource Utilization for E-Tile
Ethernet Configuration IP Core Version Logic Utilization (in ALMs) Dedicated Logic Registers M20K RAM Blocks
16x10GE-1 PTP(without TX Packet Classifier) 82,773 198,383 313
8x25GE-1 RSFEC + PTP 44,083 103,061 217
4x100GE-4 RSFEC + PTP 73,586 155,465 217
Table 6.  Ethernet Subsystem Intel FPGA IP Resource Utilization for F-Tile
Ethernet Configuration IP Core Version Logic Utilization (in ALMs) M20K RAM Blocks
1x400GE-8 RSFEC + PTP 47,723 367
4x100GE-4 AN/LT 53,112 319
16x10GE-1 AN/LT 97,605 371
16x25GE-1 AN/LT 97,726 371
1x10GE-1 AN/LT 1707.6 2739