Visible to Intel only — GUID: oag1669135745506
Ixiasoft
4.3.1.1. NOP(0x0)
4.3.1.2. get_hssi_profile for E-Tile
4.3.1.3. get_hssi_profile for F-Tile
4.3.1.4. set_hssi_profile for E-Tile
4.3.1.5. set_hssi_profile for F-Tile
4.3.1.6. read_MAC_statistic
4.3.1.7. get_mtu
4.3.1.8. set_csr for E-Tile
4.3.1.9. set_csr for F-Tile
4.3.1.10. get_csr for E-Tile
4.3.1.11. get_csr for F-Tile
4.3.1.12. enable_loopback for E-Tile
4.3.1.13. enable_loopback for F-Tile
4.3.1.14. disable_loopback for E-Tile
4.3.1.15. disable_loopback for F-Tile
4.3.1.16. Reset MAC Statistics
4.3.1.17. set_mtu for F-Tile
4.3.1.18. Ncsi_get_link_status
4.3.1.19. Reserved
4.3.1.20. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock
6.2. Clock Connections for MAC Async Client FIFO
6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
6.4. Clock Connections for SyncE Operation on E-Tile
6.5. Clock Connections for SyncE Operation on F-Tile
6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo
7.1.2. Device Feature Header Hi
7.1.3. Feature GUID_L
7.1.4. Feature GUID_H
7.1.5. Feature CSR ADDR
7.1.6. Feature CSR Size Group
7.1.7. Version
7.1.8. Feature List
7.1.9. Interface Attribute Port X Parameters
7.1.10. HSSI Command/Status
7.1.11. HSSI Control/Address
7.1.12. HSSI Read Data
7.1.13. HSSI Write Data
7.1.14. HSSI Ethernet Port X Status
Visible to Intel only — GUID: oag1669135745506
Ixiasoft
7.4. F-Tile ANLT Port Register Map
Port | Start Address | End Address |
---|---|---|
0 | 0x10000 | 0x103FF |
1 | 0x10400 | 0x107FF |
2 | 0x10800 | 0x10BFF |
3 | 0x10C00 | 0x10FFF |
4 | 0x11000 | 0x113FF |
5 | 0x11400 | 0x117FF |
6 | 0x11800 | 0x11BFF |
7 | 0x11C00 | 0x11FFF |
8 | 0x12000 | 0x123FF |
9 | 0x12400 | 0x127FF |
10 | 0x12800 | 0x12BFF |
11 | 0x12C00 | 0x12FFF |
12 | 0x13000 | 0x133FF |
13 | 0x13400 | 0x137FF |
14 | 0x13800 | 0x13BFF |
15 | 0x13C00 | 0x13FFF |
16 | 0x14000 | 0x143FF |
17 | 0x14400 | 0x147FF |
18 | 0x14800 | 0x14BFF |
19 | 0x14C00 | 0x14FFF |